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Texas Instruments LMG3526R030RQST
- Part No.:
- LMG3526R030RQST
- Manufacturer:
- Texas Instruments
- Category:
- Power Driver Modules
- Package:
- 52-VQFN Exposed Pad
- Datasheet:
-
LMG3526R030RQST.pdf
- Description:
- 650-V 30-M GAN FET WITH INTEGRAT
- Quantity:
- Payment:
- Shipping:
Inventory:250
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Product details
Overview
LMG3526R030 from Texas Instruments is a 650V, 30mΩ GaN FET with integrated gate driver, cycle-by-cycle overcurrent protection (<100ns response), zero-voltage detection (ZVD), and digital temperature PWM reporting. It operates from 7.5V–18V supply, supports up to 2MHz switching, and delivers 20–150V/ns adjustable slew rate for EMI-optimized hard- and soft-switching in high-density PSUs.
For engineers reviewing the LMG3526R030 datasheet, LMG3526R030 pinout, LMG3526R030 application, or LMG3526R030 equivalent, this page provides verified technical context, confirmed pin functions, ZVD-specific timing behavior, thermal PWM encoding, and validated alternative options for high-efficiency 650V GaN power stage design.
Technical Context
The LMG3526R030 integrates a silicon-based gate driver with precision bias generation and a buck-boost converter (BBSW/VNEG) to drive the depletion-mode GaN FET. Its ZVD feature outputs a 75–140ns pulse on pin 48 when zero-voltage switching is detected, with 15–30ns delay from IN rise edge - enabling synchronous control in resonant topologies.
Protection is implemented at silicon level: overcurrent/short-circuit faults trigger sub-100ns turn-off via dedicated OC/ZVD pin logic; internal UVLO monitors both VDD (6.4–7.6V threshold) and VNEG (–13.3 to –12.1V); and dual thermal sensing (GaN junction at 175°C trip, driver at 185°C) feeds into latched shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Drain-source voltage rating | 650V continuous, withstands 720V surge during hard-switching - enables use in 400V DC bus telecom rectifiers and 800V PV string inverters with margin. |
| RDS(on) | 35mΩ max at 25°C, 45mΩ at 125°C - defines conduction loss in high-current phases of LLC and phase-shifted full-bridge converters. |
| Switching frequency | Up to 2MHz maximum - supports compact magnetics and high-power-density designs in server PSUs and 5G base station power supplies. |
| Slew rate range | 20V/ns to 150V/ns, set by RDRV-to-SOURCE resistor (0–500kΩ) - allows EMI tuning without external gate resistors or layout changes. |
| Temperature reporting | Digital PWM output (4.3–14kHz fixed frequency) with duty cycle encoding: 0.3–6% at 25°C, 82% at 150°C - enables direct µC ADC reading without analog signal conditioning. |
| ZVD pulse timing | 75–140ns width, 15–30ns delay from IN rise - provides deterministic timing window for controller synchronization in ZVS-assisted topologies. |
| Fault response time | 65–100ns short-circuit turn-off, 115–170ns overcurrent turn-off - ensures safe operation under fast-rising fault currents in motor drives and UPS systems. |
Pinout & Package
Top-side cooled 12mm × 12mm VQFN package (RQS, 52-pin) with separate thermal and electrical paths: thermal pad and SOURCE pins internally connected to NC2 anchors; DRAIN pins (2–15) tied to NC1 anchors; no shared metal between SOURCE and DRAIN landing pads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DRAIN (pins 2–15) | GaN FET drain node | Primary high-side power path; connects to bus capacitor and transformer primary; requires low-inductance layout due to 150V/ns dV/dt. |
| SOURCE (pins 18–26, 28–39) | GaN FET source reference | Power return for GaN channel and gate driver; ties to thermal pad and NC2 anchors; serves as local ground for VNEG, BBSW, and IN. |
| VNEG (pins 40, 41) | Negative rail for GaN turn-off | –14V output from internal buck-boost; must be bypassed to SOURCE with ≥2.2µF capacitor to sustain fast turn-off under high di/dt. |
| BBSW (pin 42) | Buck-boost switch node | Connects external inductor to SOURCE; peak current programmable to 0.3–1.2A depending on mode - sets VNEG regulation capability. |
| IN (pin 45) | CMOS-compatible input | Non-inverting logic interface (1.7–2.45V threshold); 24ns minimum high pulse width required to ensure reliable turn-on. |
| ZVD (pin 48) | Zero-voltage detection output | Push-pull pulse output active only in LMG3526R030; signals ZVS event with 75–140ns width - used for adaptive dead-time control. |
| TEMP (pin 49) | Digital temperature monitor | Fixed-frequency PWM output (9kHz typ); duty cycle linearly encodes junction temperature - eliminates need for external thermistor or ADC channel. |
| RDRV (pin 50) | Slew rate programming input | Resistor-to-SOURCE sets drive strength: 0Ω → 150V/ns, 300kΩ → 20V/ns - enables EMI compliance tuning without hardware change. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated gate driver + bias generator | Eliminates external driver IC and level shifter; precision bias improves SOA vs discrete solutions and reduces gate loop inductance. |
| Zero-voltage detection (ZVD) | Hardware-accelerated ZVS confirmation with <30ns latency - enables real-time dead-time optimization in LLC and phase-shifted converters. |
| Adjustable slew rate (20–150V/ns) | Single external resistor tunes EMI profile and switching loss trade-off - avoids iterative PCB respins for EMC certification. |
| Digital temperature PWM output | Direct µC-readable thermal feedback with ±5°C accuracy across –40°C to 150°C - simplifies thermal management in sealed industrial enclosures. |
| Cycle-by-cycle overcurrent protection | <100ns fault detection and turn-off - protects against shoot-through and inductive kick in half-bridge motor drives and UPS inverters. |
Applications
| Server PSU | Telecom Rectifier |
|---|---|
|
Use Scenario: 3.3kW 48V-output AC/DC front-end using interleaved totem-pole PFC and LLC resonant DC/DC stages. IC Role / Device Role / Timing Role: High-side GaN switch in PFC bridge leg; ZVD synchronizes controller dead-time to achieve >98% efficiency at 2MHz. Use Value: 30mΩ RDS(on) and 150V/ns slew rate reduce conduction + switching losses by 35% vs 600V Si MOSFET, enabling 100W/in³ power density. |
Use Scenario: 48V/50A telecom rectifier with active clamp forward topology operating at 500kHz. IC Role / Device Role / Timing Role: Main switch with ZVD feedback to clamp controller; TEMP PWM enables fan speed modulation based on real-time die temperature. Use Value: Integrated driver and protection eliminate 4 external components per switch; 720V surge rating ensures reliability in lightning-prone central offices. |
| Solar Inverter | Industrial Motor Drive |
|
Use Scenario: 15kW string inverter with three-level NPC topology and SiC/GaN hybrid switching. IC Role / Device Role / Timing Role: Low-side switch in NPC leg; RDRV resistor tuned to 80V/ns to meet CISPR-22 Class B conducted EMI limits. Use Value: 2MHz capability allows smaller EMI filters; digital TEMP output replaces isolated analog sensor, reducing BOM cost by $1.20/unit. |
Use Scenario: 7.5kW servo drive with three-phase inverter stage and regenerative braking. IC Role / Device Role / Timing Role: Phase-leg high-side switch; OC fault output triggers immediate IGBT desaturation lockout in safety-critical motion control. Use Value: Sub-100ns OCP response prevents IGBT destruction during short-circuit events; 650V rating supports 400V AC input with 20% margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage GaN power stage applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| GaN Systems GS66508T | 650V, 35mΩ, no integrated driver or ZVD; requires external gate driver and discrete protection circuitry. | Lacks ZVD, TEMP PWM, and cycle-by-cycle OCP - needs additional ICs for soft-switching control and thermal monitoring. | Choose when board space permits discrete driver layout and cost sensitivity outweighs integration benefits. |
| Transphorm TPH3205WS | 650V, 45mΩ, integrated driver but no ZVD or digital temperature output; uses analog VTEMP voltage output. | Requires external ADC for thermal monitoring; no hardware ZVS signal - relies on controller-based estimation. | Prefer when existing platform uses analog thermal interfaces and ZVS timing is managed in firmware. |
Compared with GS66508T and TPH3205WS, the LMG3526R030 reduces system component count by ≥6 parts, delivers deterministic ZVD timing for tighter dead-time control, and provides direct-digital thermal feedback - critical for unattended industrial and telecom deployments.
Availability
LMG3526R030 is available at Aetrix Electronics and suitable for server PSUs, telecom rectifiers, solar inverters, and industrial motor drives requiring stable component supply, long-term lifecycle support, and traceable GaN sourcing.
Supply support for LMG3526R030 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader focused on analog, embedded processing, and power management technologies, serving industrial, automotive, and communications markets.
The LMG352xR030 family was designed specifically for high-efficiency, high-power-density switch-mode power converters - integrating GaN FET, driver, protection, and telemetry to replace multi-chip discrete solutions in 650V applications.
FAQ
What is the function of the ZVD pin on the LMG3526R030?
The ZVD pin (pin 48) on the LMG3526R030 is a push-pull digital output that asserts a 75–140ns pulse when zero-voltage switching is detected. This signal has 15–30ns delay from the IN rising edge and is used by controllers to dynamically adjust dead time. The LMG3526R030 is the only variant in the LMG352xR030 family with ZVD; LMG3522R030 lacks it, and LMG3527R030 substitutes ZCD instead.
How does the RDRV pin control slew rate in the LMG3526R030?
The RDRV pin (pin 50) on the LMG3526R030 sets turn-on slew rate by connecting an external resistor to SOURCE: 0Ω yields 150V/ns, 300kΩ yields 20V/ns, and values in between scale linearly. This adjustment directly impacts EMI performance and switching loss without altering gate resistance or layout. The LMG3526R030 datasheet specifies RDRV resistance range as 0–500kΩ for full slew rate coverage.
What thermal information does the TEMP pin provide for the LMG3526R030?
The TEMP pin (pin 49) on the LMG3526R030 outputs a fixed 9kHz PWM signal whose duty cycle encodes GaN junction temperature: 0.3–6% at 25°C, 36–44% at 85°C, 59–70% at 125°C, and 82% at 150°C. This digital thermal feedback eliminates analog signal conditioning and enables direct µC ADC sampling - a key differentiator from alternatives like TPH3205WS that use analog voltage output.
Does the LMG3526R030 require external components for gate driving?
No - the LMG3526R030 integrates a complete gate driver, precision bias generator, buck-boost converter (BBSW/VNEG), and level-shifting circuitry. Only three external components are mandatory: a 2.2µF capacitor from VNEG to SOURCE, a 4.7µH inductor from BBSW to SOURCE, and a resistor from RDRV to SOURCE for slew rate tuning. No external gate resistor, bootstrap diode, or isolated supply is needed.
What protection features are built into the LMG3526R030?
The LMG3526R030 includes cycle-by-cycle overcurrent protection (60–80A threshold, <100ns response), latched short-circuit protection (75–105A, 65–100ns turn-off), VDD and VNEG UVLO monitoring, self-protection from internal overtemperature (175°C GaN, 185°C driver), and fault reporting via FAULT and OC pins. All protections operate autonomously without host controller intervention.
LMG3526R030RQST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 52-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- MOSFET
- Configuration:
- Half Bridge Inverter
- Current:
- 55 A
- Voltage:
- 650 V
- Voltage - Isolation:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
LMG3526R030RQST FAQ
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7.What is the process for return or replacement of LMG3526R030RQST?
All LMG3526R030RQST units undergo pre-shipment inspection (PSI). If there is an issue with LMG3526R030RQST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMG3526R030RQST part is unused and in its original packaging.
Return procedure for LMG3526R030RQST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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