Texas Instruments LMK61E07-SIAT

Overview

LMK61E07-SIAT from Texas Instruments is an ultra-low jitter (90-fs RMS typical @ >100 MHz), programmable oscillator with integrated fractional-N PLL, 4.6–5.6 GHz VCO, and factory-configurable EEPROM. It delivers LVPECL/LVDS/HCSL differential outputs up to 1 GHz, ±25 ppm total frequency tolerance, and glitch-less frequency margining from ±1000 ppm - deployed in FPGA clocking, 5G baseband units, and broadcast video timing systems.

For engineers reviewing the LMK61E07-SIAT datasheet, LMK61E07-SIAT pinout, LMK61E07-SIAT application, or LMK61E07-SIAT equivalent, key selection criteria include RMS jitter performance at target output frequency, output format compatibility (LVPECL vs. LVDS vs. HCSL), I²C programmability for in-system tuning, and EEPROM persistence for reliable power-on startup without external configuration.

Technical Context

The LMK61E07-SIAT integrates a 50-MHz crystal, fractional-N PLL with delta-sigma noise shaping, and a 4.6–5.6 GHz VCO. Its PLL supports both integer-N (≤200 fs RMS jitter) and fractional-N (≤300 fs RMS jitter) modes, with PFD frequencies selectable at 12.5 MHz (xDSL-compliant <1 ppb steps) or 100 MHz (broadcast video-compliant <5.2 ppb steps).

Output buffering is configurable for LVPECL (up to 1 GHz), LVDS (up to 900 MHz), or HCSL (up to 400 MHz), each with matched differential swing and duty cycle (45–55%). Power supply rejection is –70 dBc across 50 kHz–1 MHz, enabled by on-chip LDOs isolating analog PLL rails from digital I²C and EEPROM domains.

Key Specifications

Pinout & Package

LMK61E07-SIAT uses a 7.0 mm × 5.0 mm, 6-pin QFM (SIA) package with exposed thermal pad. Pin assignment is validated per TI SNAS722B Rev B (August 2023): SDA and SCL are open-drain I²C lines requiring external pull-ups; OUTP/OUTN form a fully differential clock pair; VDD and GND provide dedicated power/ground routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si5341-A01A-GM, LMK61E07-SIAT offers superior single-output jitter and simpler EEPROM-based startup, while LMK61E2-156M25 trades flexibility for lower unit cost and reduced qualification overhead in fixed-frequency deployments.

Availability

LMK61E07-SIAT is available at Aetrix Electronics and suitable for 5G infrastructure, broadcast video equipment, enterprise storage controllers, and high-performance FPGA-based systems requiring stable component supply across extended product lifecycles.

Supply support for LMK61E07-SIAT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in precision timing and signal integrity.

The LMK61E07 belongs to TI's PLLatinum™ programmable oscillator family, engineered specifically for ultra-low jitter, system-level configurability, and EEPROM persistence in telecom, computing, and test equipment applications.

FAQ

What output formats does LMK61E07-SIAT support, and how are they selected?

LMK61E07-SIAT supports LVPECL (up to 1 GHz), LVDS (up to 900 MHz), and HCSL (up to 400 MHz) outputs. Format selection is performed via I²C register writes to the OUTPUT_FORMAT bits (Register 0x0A[5:4]) and requires corresponding external termination (e.g., 150 Ω for LVPECL, 100 Ω differential for LVDS). The setting persists in EEPROM after programming.

How does the internal EEPROM function, and what parameters can it store?

The internal EEPROM stores the complete register configuration, including output frequency, format, divider values, and startup enable state. After power-on, the device automatically loads these settings and begins oscillating within 10 ms. Users program EEPROM via I²C using the EEPROM_WRITE_ENABLE sequence followed by register writes and a final EEPROM commit command (Register 0x00[7]).

What is the maximum frequency margining resolution, and how is it achieved?

LMK61E07-SIAT achieves <1 ppb resolution in coarse margining (PFD = 12.5 MHz) and <5.2 ppb in fine margining (PFD = 100 MHz), using fractional-N PLL with delta-sigma modulation. Margining is executed via I²C writes to the PLL_FRACNUM registers, updating the feedback divider without output glitches - verified in TI SNAS722B Section 6.10.

Does LMK61E07-SIAT require external loop filter components?

No. LMK61E07-SIAT integrates a passive loop filter within the IC, eliminating external resistors and capacitors. The loop filter coefficients (R2, C1, C2) are programmable via I²C registers (0x20–0x22) and optimized for 400-kHz bandwidth. This simplifies PCB layout and improves repeatability across manufacturing lots.