Texas Instruments LMK61E2-SIAT

Overview

LMK61E2-SIAT from Texas Instruments is an ultra-low jitter (90 fs RMS typical >100 MHz), programmable oscillator with integrated fractional-N PLL, 4.6–5.6 GHz VCO, and factory-configured 156.25 MHz LVPECL output. It features on-chip EEPROM for self-startup, I²C programmability, and supports LVPECL (≤1 GHz), LVDS (≤900 MHz), or HCSL (≤400 MHz) outputs in a 7 mm × 5 mm QFM-8 package. Used in FPGA clocking, network line cards, and high-speed serial interfaces requiring sub-200 fs jitter.

For engineers reviewing the LMK61E2-SIAT datasheet, LMK61E2-SIAT pinout, LMK61E2-SIAT application, or LMK61E2-SIAT equivalent, key selection criteria include RMS jitter performance at target frequency, output format compatibility (LVPECL/LVDS/HCSL), EEPROM programmability for custom startup configuration, PSRR (–70 dBc), and industrial temperature range (–40°C to +85°C).

Technical Context

The LMK61E2-SIAT implements a fractional-N PLL architecture with integrated 50 MHz crystal and VCO spanning 4.6–5.6 GHz, enabling precise synthesis of common reference clocks (e.g., 156.25 MHz, 161.1328125 MHz). Its dual-mode PLL supports both integer-N (≤200 fs RMS jitter) and fractional-N (≤300 fs RMS jitter) operation.

Power conditioning includes dedicated LDOs isolating analog PLL supplies from digital I²C/EEPROM domains, delivering –70 dBc PSRR from 50 kHz to 1 MHz. Output stage is a universal differential buffer configurable via register settings for LVPECL, LVDS, or HCSL drive, with fine/coarse frequency margining accessible over I²C.

Key Specifications

Pinout & Package

The LMK61E2-SIAT is housed in a 7 mm × 5 mm, 8-pin QFM (SIA) package with exposed thermal pad. Pin 1 is ADD; pin 3 is GND; pin 6 is VDD; pins 4 and 5 are differential outputs (OUTP/OUTN); pin 8 is SCL; pin 7 is SDA; pin 1 is OE. All digital control pins are LVCMOS-compatible with internal pull-ups on OE.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si5338A-D-GM, LMK61E2-SIAT offers lower jitter and smaller footprint but single-output capability; compared with LMK61E0M-SIAT, it trades minor jitter increase (90 vs. 100 fs) for full in-system programmability and EEPROM flexibility.

Availability

LMK61E2-SIAT is available at Aetrix Electronics and suitable for FPGA clocking, 100G Ethernet line cards, and 5G baseband units requiring stable component supply, guaranteed long-term availability, and traceable sourcing for industrial and telecom deployments.

Supply support for LMK61E2-SIAT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and clock solutions, with leadership in high-performance timing devices for communications and computing.

The LMK61E2 belongs to TI's PLLatinum™ programmable oscillator family, designed specifically for applications demanding ultra-low jitter, EEPROM-based self-startup, and flexible output format selection in space-constrained infrastructure equipment.

FAQ

What is the default output configuration of the LMK61E2-SIAT at power-up?

The LMK61E2-SIAT powers up with factory-programmed EEPROM settings generating 156.25 MHz LVPECL output. This occurs automatically without host I²C interaction. The output remains enabled unless OE is pulled low, and all internal registers retain their EEPROM-loaded values until modified via I²C.

Can the LMK61E2-SIAT generate non-standard frequencies like 161.1328125 MHz?

Yes - the LMK61E2-SIAT supports arbitrary frequencies within its output range using its fractional-N PLL. 161.1328125 MHz is explicitly characterized in the datasheet (Section 5.18) with verified phase noise and jitter performance. Configuration is done via I²C register writes or TI's Clock Architect software.

Does the LMK61E2-SIAT require external loop filter components?

No - the LMK61E2-SIAT integrates a passive loop filter within the PLL block. No external resistors or capacitors are needed for PLL stabilization. Layout guidance emphasizes clean VDD decoupling and controlled-impedance differential trace routing, but no loop filter BOM items are required.

How is the I²C address determined for the LMK61E2-SIAT?

The I²C slave address is set by the ADD pin (Pin 2): tied to GND = 0x54, floating = 0x55, tied to VDD = 0x56. This allows up to three LMK61E2-SIAT devices on the same I²C bus. Address selection is latched at power-up and remains fixed until next reset.