Texas Instruments LMK61E08-SIAR

Overview

LMK61E08-SIAR from Texas Instruments is an ultra-low jitter (90-fs RMS typical), programmable oscillator with integrated 50-MHz crystal, fractional-N PLL, and on-chip EEPROM. It delivers LVPECL/LVDS/HCSL differential outputs up to 1 GHz, operates at 3.3 V, and supports glitchless frequency margining ±1000 ppm - deployed in FPGA clocking, 156.25-MHz Ethernet PHY timing, and broadcast video reference generation.

For engineers reviewing the LMK61E08-SIAR datasheet, LMK61E08-SIAR pinout, LMK61E08-SIAR application, or LMK61E08-SIAR equivalent, key selection criteria include sub-200-fs RMS jitter (12 kHz–20 MHz), I²C-programmable output format and startup frequency, PSRR of –70 dBc, industrial temperature range (–40°C to +85°C), and 7-mm × 5-mm QFM package compatibility with high-density PCB layouts.

Technical Context

The LMK61E08-SIAR integrates a 50-MHz fundamental-mode crystal with a fractional-N PLL featuring a 4.6–5.6-GHz VCO, configurable R-divider (×1/×4), reference doubler (enabled/disabled), and 9-bit integer output divider (5–511). Its phase-frequency detector runs at 12.5 MHz (R=4, doubler off) or 100 MHz (R=1, doubler on), enabling <1-ppb or <5.2-ppb frequency step resolution for xDSL and broadcast video compliance.

Power conditioning uses isolated on-chip LDOs for analog (PLL/VCO) and digital (I²C/interface) domains, achieving –70 dBc PSRR across 50 kHz–1 MHz supply ripple. The device boots autonomously from EEPROM-configured defaults and supports in-system reprogramming via Fast Mode I²C (up to 1000 kHz) with open-drain SCL/SDA requiring external pullups to VDD.

Key Specifications

Pinout & Package

LMK61E08-SIAR is housed in a 7.00 mm × 5.00 mm, 6-pin QFM (SIA) package with exposed thermal pad. Pin 1 (SDA) and Pin 2 (SCL) are open-drain I²C interfaces requiring external pullup resistors to VDD; Pins 4 (OUTP) and 5 (OUTN) form the differential clock output pair; Pin 3 (GND) is system ground; Pin 6 (VDD) supplies 3.3 V.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si5341-A01AGM, LMK61E08-SIAR offers smaller footprint and self-contained operation but lacks multi-output capability; versus LMK61E2-156M25SIAR, it trades fixed-frequency simplicity for full programmability and margining - making it optimal for prototyping, DVT, and mixed-standard platforms.

Availability

LMK61E08-SIAR is available at Aetrix Electronics and suitable for 100G Ethernet line cards, FPGA-based test equipment, broadcast video timing, and medical ultrasound beamforming requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LMK61E08-SIAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.

The LMK61E08-SIAR belongs to TI's PLLatinum™ programmable oscillator family, designed specifically for high-performance timing applications demanding ultra-low jitter, flexible output formats, and robust power supply immunity in space-constrained systems.

FAQ

What is the default startup frequency of the LMK61E08-SIAR?

The LMK61E08-SIAR powers up with a factory-programmed default frequency of 70.656 MHz, generated from its internal 50-MHz crystal and preconfigured PLL settings stored in on-chip EEPROM. This occurs autonomously without host intervention or I²C communication.

Can the LMK61E08-SIAR operate with LVDS output at 900 MHz?

Yes - the LMK61E08-SIAR supports LVDS output up to 900 MHz, with guaranteed 300–480 mV differential swing, 45–55% duty cycle, and 150–250 ps rise/fall time (20%–80%). Operation at 900 MHz requires proper 100-Ω differential termination and layout adherence to TI's recommended routing guidelines.

How is frequency margining implemented without output glitches?

Frequency margining is achieved by dynamically updating the PLL feedback divider (INT/NUM/DEN) or output divider registers via I²C. The device uses a phase-frequency detector with continuous phase tracking and seamless divider transitions, ensuring no output interruptions or frequency spikes during adjustment - verified per TI's SNAS805 test methodology.

Does the LMK61E08-SIAR require external components for basic operation?

Yes - external 4.7-kΩ pullup resistors on SCL and SDA pins are mandatory for I²C communication; a 10-nF ceramic capacitor must be placed within 2 mm of the VDD pin for power integrity; and differential output lines require 100-Ω termination (LVDS/LVPECL) or 50-Ω to ground per leg (HCSL), as specified in TI's layout guidelines.