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Texas Instruments LP3905SD-00/NOPB
- Part No.:
- LP3905SD-00/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 14-WFDFN Exposed Pad
- Datasheet:
-
LP3905SD-00/NOPB.pdf
- Description:
- IC PWR MANAGEMENT DUAL 14WSON
- Quantity:
- Payment:
- Shipping:
Inventory:4,862
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Product details
Overview
LP3905SD-00/NOPB from Texas Instruments is a highly integrated power management unit (PMU) for low-power handheld systems, featuring two 600mA synchronous buck regulators and two 150mA low-noise LDOs in a single 14-pin WSON package. It delivers fixed-output voltages (LDO1/LDO2: 1.5V–3.3V; Bucks: adjustable or factory-set), supports auto-switching PFM-PWM mode, and provides ±4% buck output accuracy and 13.5µVrms LDO noise - enabling efficient baseband processor and peripheral I/O power in battery-constrained devices.
For engineers reviewing the LP3905SD-00/NOPB datasheet, LP3905SD-00/NOPB pinout, LP3905SD-00/NOPB application, or LP3905SD-00/NOPB equivalent, this page delivers verified technical context, validated pin functions, real-world application mappings, and confirmed alternative options - all grounded in TI's SNVS374D revision May 2013 specification and official WSON (NHL0014B) package documentation.
Technical Context
The LP3905SD-00/NOPB implements voltage-mode PWM control with 2MHz fixed-frequency operation and automatic PFM entry below ~50–115mA (depending on VIN), achieving up to 90% efficiency at 300mA. Its dual-buck architecture uses internal PFET/NFET synchronous rectification with 380mΩ/250mΩ typical RDS(on), while the LDOs feature 80mV dropout at 100mA and 70dB PSRR at 1kHz.
Power sequencing is managed via independent EN1 (controls Buck1 + both LDOs) and EN2 (controls Buck2 only), with built-in soft-start, thermal shutdown (160°C), UVLO (2.7–3.1V), and current limiting (650–1220mA peak). All regulators share a common 3V–5.5V input range across VIN1 (buck supply) and VIN2 (LDO supply), requiring tied inputs per TI's power-up specification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 600mA per channel - supports high-current processor cores or memory interfaces without external boost stages. |
| LDO Output Current | 150mA per channel with 1.0µF output capacitor - sufficient for I/O banks, sensors, or FPGA configuration logic. |
| Switching Frequency | 2MHz (typical) - enables use of compact 2.2µH inductors and reduces EMI filtering burden in space-constrained PCBs. |
| LDO Noise | 13.5µVrms - meets stringent analog/RF supply requirements for audio codecs or RF front-end biasing. |
| Output Voltage Accuracy | ±4% for bucks, ±3% for LDOs over full line/load/temp - ensures reliable operation of voltage-sensitive digital logic. |
| Package | 14-pin WSON (4mm × 4mm × 0.8mm, NHL0014B) - surface-mount, thermally enhanced die-attach pad (SGND) for industrial-grade thermal dissipation (θJA = 37.3°C/W). |
| Enable Control | EN1 enables Buck1 + LDO1/LDO2; EN2 independently enables Buck2 - allows flexible power sequencing for multi-rail SoCs. |
Pinout & Package
LP3905SD-00/NOPB is housed in a thermally optimized 14-pin WSON package (TI package code NHL0014B) with exposed die-attach pad (SGND) for enhanced heat transfer. Pin numbering follows standard top-view orientation with Pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN2 | Buck2 enable input | Active-high logic control; enables/disables Buck2 independently of other rails. |
| 2 - TGND | Thermal ground reference | Internal tie to substrate; must be connected to SGND plane for thermal stability and noise immunity. |
| 3 - LDO2 | LDO2 regulated output | Delivers fixed or adjustable 1.5–3.3V at up to 150mA; low-noise rail for sensitive analog circuitry. |
| 4 - VIN2 | LDO input supply | 3–5.5V input shared by both LDOs; must be tied to VIN1 per TI's power-up requirement. |
| 5 - LDO1 | LDO1 regulated output | Delivers fixed or adjustable 1.5–3.3V at up to 150mA; commonly used for core logic or interface I/O. |
| 6 - GND | LDO ground return | Common ground for LDO1/LDO2; requires low-impedance connection to system ground plane. |
| 7 - EN1 | Buck1 + LDOs enable input | Active-high logic control; powers up Buck1, LDO1, and LDO2 simultaneously. |
| 8 - FB1 | Buck1 feedback input | 0.5V reference point for adjustable output; sets VOUT1 = 0.5V × (1 + R1/R2) in external resistor divider. |
| 9 - GND_B1 | Buck1 ground return | Dedicated ground for Buck1 switching loop; minimizes noise coupling into LDO or analog sections. |
| 10 - SW1 | Buck1 switch node | Connects to external 2.2µH inductor and output capacitor; carries high di/dt switching current. |
| 11 - VIN1 | Buck input supply | 3–5.5V input shared by both bucks; must be tied to VIN2 for proper startup sequencing. |
| 12 - SW2 | Buck2 switch node | Connects to second 2.2µH inductor and output capacitor; isolated from SW1 to prevent cross-talk. |
| 13 - GND_B2 | Buck2 ground return | Dedicated ground for Buck2 switching loop; routed separately from GND_B1 and LDO grounds. |
| 14 - FB2 | Buck2 feedback input | 0.5V reference point for adjustable output; sets VOUT2 = 0.5V × (1 + R1/R2) independently of FB1. |
| DAP - SGND | Exposed thermal pad | Must be soldered to solid copper thermal plane; primary path for junction-to-board heat transfer. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-switching PFM-PWM mode | Extends battery life in standby by reducing quiescent current to 16µA (sleep mode) while maintaining fast wake-up response. |
| Integrated synchronous rectification | Eliminates external Schottky diodes; achieves >90% efficiency at 300mA with internal 380mΩ PFET / 250mΩ NFET switches. |
| Independent enable control | EN1 and EN2 allow staggered power-up (50µs Buck2 delay) to limit inrush current from single-cell Li-ion batteries. |
| Low-noise LDO regulation | 13.5µVrms output noise and 70dB PSRR at 1kHz enable clean power delivery to RF transceivers and audio DACs. |
| Robust protection suite | Includes thermal shutdown (160°C), current limiting (1220mA peak), UVLO (2.7V), and soft-start - prevents damage during fault conditions. |
Applications
| Baseband Processor Power | Peripheral I/O Supply |
|---|---|
Use Scenario: Powering ARM-based baseband processors in GSM/UMTS handsets requiring multiple voltage rails (e.g., 1.2V core, 1.8V I/O, 2.8V RF). IC Role / Device Role / Timing Role: LP3905SD-00/NOPB delivers sequenced, low-noise power to processor domains using EN1/EN2 timing control and independent buck/LDO outputs. Use Value: Eliminates need for four discrete regulators; reduces BOM count and PCB area while meeting tight transient response specs (<30mV load step deviation). |
Use Scenario: Supplying voltage to camera modules, touch controllers, and USB PHYs in portable media players. IC Role / Device Role / Timing Role: LP3905SD-00/NOPB LDO1/LDO2 provide stable, low-noise 1.8V/2.8V rails decoupled from noisy buck switching nodes. Use Value: PSRR >70dB at 1kHz suppresses switching noise from bucks, preventing image artifacts or touch jitter in signal-sensitive peripherals. |
| FPGA Configuration Logic | Audio Codec Biasing |
Use Scenario: Powering configuration SRAM, I/O banks, and auxiliary logic in low-power FPGAs used in wearable health monitors. IC Role / Device Role / Timing Role: LP3905SD-00/NOPB Buck1 supplies 1.2V core, Buck2 supplies 2.5V I/O, and LDO2 supplies 3.3V configuration rail - all from single Li-ion cell. Use Value: 600mA per buck supports FPGA dynamic loads; ±4% accuracy ensures reliable bitstream loading and I/O signaling integrity. |
Use Scenario: Delivering ultra-low-noise bias to stereo audio DACs and headphone amplifiers in Bluetooth headsets. IC Role / Device Role / Timing Role: LP3905SD-00/NOPB LDO1 provides 1.8V analog supply with 13.5µVrms noise, isolated from digital switching paths via dedicated GND_B1/GND_B2. Use Value: Meets THD+N <−90dB requirements for high-fidelity playback; eliminates need for post-LDO RC filtering stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Three bucks + two LDOs; higher integration but larger 48-pin QFN; no PFM mode; 1.2MHz switching. | Targets higher-power OMAP/ARM platforms; less suitable for ultra-low-IQ standby. | Choose when needing third buck rail or higher current (1A bucks); avoid if board space or PFM battery life are critical. |
| MAX8649ETG+ | Two bucks + one LDO; 3MHz switching; 400mA bucks; no independent EN2; TQFN-24 package. | Optimized for compact wearables; lacks second LDO and separate Buck2 enable. | Choose for minimal footprint where dual-LDO redundancy isn't required; verify LDO noise spec (not published) before audio use. |
Compared with TPS65023RSBR and MAX8649ETG+, the LP3905SD-00/NOPB uniquely balances ultra-low-noise LDOs, independent Buck2 enable, and PFM efficiency - making it optimal for battery-limited handhelds requiring precise sequencing and analog-clean power without over-engineering.
Availability
LP3905SD-00/NOPB is available at Aetrix Electronics and suitable for baseband processor power, peripheral I/O supply, FPGA configuration logic, and audio codec biasing requiring stable component supply across consumer electronics, medical wearables, and industrial handheld designs.
Supply support for LP3905SD-00/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in battery-powered system design.
The LP3905SD-00/NOPB belongs to TI's low-power PMU product line, engineered specifically for single-cell Li-ion and multi-cell NiMH/NiCd powered handhelds - emphasizing efficiency at light loads, sequencing flexibility, and noise isolation for mixed-signal SoC applications.
FAQ
What is the recommended input voltage range for LP3905SD-00/NOPB?
The LP3905SD-00/NOPB requires VIN1 and VIN2 to be tied together and operated between 3.0V and 5.5V. Operation below 3.0V risks UVLO activation (VUVLO-R = 2.7–3.1V), while exceeding 5.5V violates absolute maximum ratings. TI specifies that both inputs must be connected at all times for correct power-up behavior, and the device is optimized for single Li-ion (3.0–4.2V) or three-cell NiMH (3.6–4.5V) sources.
Does LP3905SD-00/NOPB support adjustable output voltages for its buck regulators?
Yes, LP3905SD-00/NOPB supports adjustable buck outputs via external resistor dividers on FB1 and FB2 pins. Each feedback network sets VOUT = 0.5V × (1 + R1/R2), enabling outputs from 1.0V to 3.3V. The datasheet provides exact resistor and capacitor values for common voltages (e.g., 1.5V, 2.5V, 3.3V), and recommends a 200kΩ R2FB to balance noise immunity and quiescent current draw.
How does the enable pin configuration work on LP3905SD-00/NOPB?
LP3905SD-00/NOPB uses two independent enable pins: EN1 controls Buck1, LDO1, and LDO2 simultaneously, while EN2 controls only Buck2. This allows flexible sequencing - for example, powering core logic first (via EN1), then enabling a peripheral rail (via EN2) after stabilization. TI specifies a 50µs delay between Buck1 and Buck2 startup when both enables are asserted concurrently to limit inrush current.
What thermal management considerations apply to LP3905SD-00/NOPB?
LP3905SD-00/NOPB uses a WSON package with an exposed SGND pad (DAP) that must be soldered to a minimum 100mm² copper thermal plane. TI specifies θJA = 37.3°C/W for the NHL0014B package, and thermal shutdown activates at 160°C with 20°C hysteresis. To maintain reliability under 600mA buck loads, designers must include ≥4 thermal vias under the DAP and avoid routing noisy signals beneath the pad.
Can LP3905SD-00/NOPB operate with ceramic output capacitors smaller than 10µF?
Yes - LP3905SD-00/NOPB supports reduced output capacitance depending on load: 0.47µF is sufficient for ≤100mA LDO output, and 1.0µF suffices for ≤150mA LDO output. For bucks, TI validates performance with 10µF, but the control loop remains stable down to 4.7µF with appropriate compensation. However, lower capacitance increases output ripple and degrades load-transient response, so 10µF is recommended for production designs per the typical application circuit.
LP3905SD-00/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-WFDFN Exposed Pad
- Packaging:
- Cut Tape (CT)
- Product Status:
- Obsolete
- Applications:
- Handheld/Mobile Devices
- Current - Supply:
- -
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-WSON (4x4)
LP3905SD-00/NOPB FAQ
1.How can I place an order for LP3905SD-00/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3905SD-00/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3905SD-00/NOPB reliable?
The price and inventory of LP3905SD-00/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3905SD-00/NOPB is usually 5 days.
3.What payment methods are accepted for LP3905SD-00/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3905SD-00/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3905SD-00/NOPB?
LP3905SD-00/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3905SD-00/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3905SD-00/NOPB?
For technical support, including LP3905SD-00/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3905SD-00/NOPB requirements.
6.How does Aetrix verify that LP3905SD-00/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3905SD-00/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3905SD-00/NOPB meets industry standards.
7.What is the process for return or replacement of LP3905SD-00/NOPB?
All LP3905SD-00/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3905SD-00/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3905SD-00/NOPB part is unused and in its original packaging.
Return procedure for LP3905SD-00/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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