Texas Instruments LP3905SDX-A3

Overview

LP3905SDX-A3 from Texas Instruments is a dual-buck + dual-LDO power management unit (PMU) for low-power handheld applications. It integrates two 600mA synchronous buck regulators (2MHz fixed PWM or auto PFM-PWM), two 150mA low-noise LDOs (±3% accuracy, 13.5µVrms noise), and independent enable control (EN1 for Buck1/LDO1/LDO2; EN2 for Buck2). It powers baseband processors and I/O in battery-powered portable devices.

For engineers reviewing the LP3905SDX-A3 datasheet, LP3905SDX-A3 pinout, LP3905SDX-A3 application, or LP3905SDX-A3 equivalent, key selection factors include its 14-pin WSON package, dual-enable sequencing, ±4% buck output accuracy, thermal/current protection, and support for Li-Ion/NiMH input (3V–5.5V).

Technical Context

The LP3905SDX-A3 employs voltage-mode PWM control with input feed-forward for stable line/load regulation and supports automatic transition between 2MHz PWM (≥80mA load) and discontinuous-conduction PFM mode (<80mA) to maximize battery life. Its internal 0.5V feedback reference enables precise output adjustment via external resistor dividers on FB1/FB2.

Buck regulation uses internal PFET/NFET synchronous rectification (RDSON_P = 500mΩ typ, RDSON_N = 400mΩ typ) with peak current limiting (1000mA typ) and soft-start (stepwise current limit ramp). LDOs feature 80mV dropout at 100mA, 70dB PSRR at 1kHz, and active pulldown when disabled.

Key Specifications

Pinout & Package

LP3905SDX-A3 is housed in a thermally enhanced 14-pin WSON package (4mm × 4mm × 0.8mm, package code NHL0014B) with exposed die attach pad (SGND) for improved thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMU applications.

Compared with TPS65023RSBR, LP3905SDX-A3 offers smaller footprint and lower quiescent current but lacks programmability and higher current capability; compared with LP3907SDX, it provides design flexibility through adjustable outputs at the cost of two extra external resistors per buck.

Availability

LP3905SDX-A3 is available at Aetrix Electronics and suitable for baseband processor power, peripheral processor (video/audio) supplies, FPGA I/O bank regulation, and low-power sensor hub applications requiring stable component supply across production lifecycles.

Supply support for LP3905SDX-A3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions with broad industrial, automotive, and consumer reach.

The LP3905SDX-A3 belongs to TI's low-power handheld PMU product line, designed specifically to consolidate power rails in space-constrained, battery-operated devices like smartphones, PDAs, and portable medical instruments.

FAQ

What input voltage range does the LP3905SDX-A3 support?

The LP3905SDX-A3 supports an input voltage range of 3V to 5.5V on both VIN1 and VIN2 pins. Both inputs must be tied together for proper power-up sequencing and UVLO operation. Operation below 3V is not guaranteed, and absolute maximum rating is 6.0V. This range accommodates single-cell Li-Ion batteries (2.8V–4.2V) and three-cell NiMH/NiCd packs (3.6V–4.5V), making LP3905SDX-A3 suitable for mainstream handheld platforms.

How does the LP3905SDX-A3 manage power sequencing between its rails?

The LP3905SDX-A3 uses two dedicated enable pins: EN1 activates Buck1, LDO1, and LDO2 simultaneously, while EN2 independently controls Buck2. When both enables are asserted together, Buck2 startup is delayed by ~50µs to reduce inrush current. LDOs only power up after Buck1 is stable. This built-in sequencing eliminates external timing circuitry and ensures safe, repeatable power-up in multi-rail systems using LP3905SDX-A3.

Can the LP3905SDX-A3 buck outputs be adjusted, and what is required?

Yes, the LP3905SDX-A3 buck outputs are adjustable via external resistor dividers on FB1 and FB2 pins, each referenced to an internal 0.5V feedback voltage. For example, a 360kΩ resistor from VOUT to FB1 and 180kΩ from FB1 to GND sets a 1.5V output. The datasheet provides standard resistor values for outputs from 1.0V to 3.3V. No additional compensation components are needed for most configurations, enabling flexible voltage assignment without redesigning the LP3905SDX-A3 core layout.

What thermal considerations apply to the LP3905SDX-A3 in high-load operation?

The LP3905SDX-A3 features thermal shutdown at 160°C junction temperature with 20°C hysteresis and has a junction-to-ambient thermal resistance (θJA) of 37.3°C/W in the NHL0014B WSON package. To maintain reliability at full 600mA buck load, the PCB must include a solid thermal pad connected to ≥4 thermal vias under the exposed DAP (SGND), and ambient temperature should remain ≤85°C. Derating is required above 60°C ambient if power dissipation exceeds 0.5W - verified using TA-MAX = 160°C − (θJA × PD).

Does the LP3905SDX-A3 support forced PWM mode, or is PFM automatic?

The LP3905SDX-A3 automatically transitions between PWM and PFM modes based on load: it operates in 2MHz PWM mode above ~80mA and switches to discontinuous-conduction PFM mode below that threshold to minimize quiescent current (16µA typ in sleep). There is no pin or register to force continuous PWM - the mode selection is fully internal and optimized for battery life. This behavior is inherent to the LP3905SDX-A3 architecture and cannot be overridden by external control.