Texas Instruments LP3910SQ-AP/NOPB
- Part No.:
- LP3910SQ-AP/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LP3910SQ-AP/NOPB.pdf
- Description:
- IC PWR MGMT W/CHARGER 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,861
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP3910SQ-AP/NOPB from Texas Instruments is a highly integrated power management IC (PMIC) designed for HDD-based portable media players, featuring two programmable LDOs (LDO1: 2.8 V, LDO2: 1.5 V), two DVS buck converters (Buck1: 1.45 V, Buck2: 1.8 V), a wide-load-range buck-boost (3.3 V), an 8-bit dual-slope ADC, and a linear Li-ion charger with USB/adapter input support and battery temperature monitoring.
For engineers reviewing the LP3910SQ-AP/NOPB datasheet, LP3910SQ-AP/NOPB pinout, LP3910SQ-AP/NOPB application, or LP3910SQ-AP/NOPB equivalent, this device serves as a system-level power solution requiring coordinated sequencing, battery health supervision, multi-rail voltage scaling, and I²C-programmable configuration in space-constrained portable audio/video platforms.
Technical Context
The LP3910SQ-AP/NOPB integrates five independent DC-DC regulation paths - two low-noise LDOs (LDO1/LDO2), two high-efficiency PWM buck converters (Buck1/Buck2) with dynamic voltage scaling, and a wide-load-range buck-boost converter - all managed via a single 400-kHz I²C interface. Its internal 8-bit dual-slope ADC monitors battery voltage, thermistor, charge current, and system inputs with ±1 LSB INL/DNL accuracy.
Battery management includes constant-current/constant-voltage charging (100 mA full-rate), selectable termination voltages (4.1 V / 4.2 V / 4.38 V), 0.35% VTERM accuracy, pre-qualification at 50 mA, and thermal regulation up to 125°C junction. Power-on/off sequencing is controlled through dedicated digital inputs (ONOFF, POWERACK) and programmable turn-on delays (T1–T5).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LDO1 Output | 2.8 V nominal; programmable 1.2–3.3 V in 100-mV steps for general-purpose core/logic rails |
| LDO2 Output | 1.5 V nominal; low-noise analog supply with 50 µVRMS noise (10 Hz–100 kHz) |
| Buck1 Output | 1.45 V nominal; DVS-capable PWM converter supporting dynamic core voltage scaling |
| Buck-Boost Output | 3.3 V nominal; maintains regulated output across wide input range (2.5–6 V) for USB/adapter/battery sources |
| Charger Full-Rate Current | 100 mA from wall adapter; supports USB 100/500/800 mA limits with pre-qualification at 50 mA |
| ADC Resolution | 8-bit dual-slope; measures battery voltage, TS thermistor, ISENSE, and auxiliary analog inputs with ±1 LSB INL/DNL |
| I²C Interface | 400-kHz compatible; fixed chip address 0x60 (hex); supports register-level control of all power rails and status |
Pinout & Package
LP3910SQ-AP/NOPB is housed in a thermally enhanced 6 mm × 6 mm × 0.8 mm 48-pin WQFN package with exposed thermal pad (NJV). The layout separates analog (AGND), digital (DGND), and high-current grounds (BBGND1/2, BCKGND1/2) to minimize noise coupling and optimize thermal dissipation under sustained load.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TS | Battery temperature sense input | Analog input for 100-kΩ thermistor; enables battery thermal profiling and charge safety cutoff |
| VIN1, VIN2, VIN3, VIN4, VDD1–3, USBPWR, CHG_DET | Multiple power inputs | Independent supply pins for LDOs, bucks, buck-boost, USB, and wall adapter detection; require external shorting per function group |
| VLDO1, VLDO2, VBUCK1, VBUCK2, VBBOUT | Regulated outputs | Five distinct power rails with dedicated feedback (VFB1/VFB2/VBBFB) and ground return paths |
| I2C_SDA / I2C_SCL | I²C bidirectional data/clock | 400-kHz interface for real-time rail programming, status readback, and fault logging |
| IRQB / NRST / ONSTAT / CHG / STAT | Digital status outputs | Open-drain interrupt, reset, power-state indicator, and dual-color LED drivers (red/green) for charge state |
| ONOFF / POWERACK / LDO2EN / BUCK1EN | Digital enable/control inputs | Level- or edge-triggered sequencing controls; support hardware-initiated power-up/down with configurable delays |
Key Features
| Feature | Design Value |
|---|---|
| Programmable multi-rail power architecture | Five independently configurable rails (2 LDOs + 2 bucks + 1 buck-boost) with I²C register access for voltage, timing, and mode control |
| Integrated battery management | Linear CC/CV charger with 4.1–4.38 V termination, 0.35% accuracy, 50 mA pre-qual, and 10-hour safety timer |
| System-level supervision | 8-bit ADC with four analog inputs, thermal interrupt (115°C), battery low threshold (2.5 V), and 8-source IRQB |
| Robust thermal design | Thermal shutdown at 160°C (20°C hysteresis); RθJA = 25°C/W; supports 1.6 W max power dissipation at TA = 70°C |
| Sequencing flexibility | Configurable turn-on/off delays (T1–T5) per rail; level/edge-triggered ONOFF; POWERACK handshake for safe power transitions |
Applications
| Hard Drive-Based Media Players | Portable Navigation Devices |
|---|---|
|
Use Scenario: Portable GPS units with rotating HDD storage, real-time map rendering, and audio guidance. IC Role / Device Role / Timing Role: Central PMIC managing HDD spindle motor voltage (buck-boost), baseband processor core (Buck1), RF/analog section (LDO2), and battery telemetry. Use Value: Enables precise DVS for CPU throttling during navigation computation while maintaining stable 3.3 V for HDD interface and low-noise 1.5 V for GPS RF front-end. |
Use Scenario: In-vehicle portable navigation systems powered by car USB or internal Li-ion battery. IC Role / Device Role / Timing Role: Dual-source power manager handling USB 500 mA charging, battery backup, and sequenced rail activation for display, GPS, and audio subsystems. Use Value: Supports seamless source handover between USB and battery without brownout; uses ADC to monitor battery health and prevent deep discharge during extended route calculation. |
| Portable Gaming Players | Audio/Video Media Players |
|
Use Scenario: Handheld gaming consoles with HDD storage, LCD display, stereo audio, and tactile feedback. IC Role / Device Role / Timing Role: System power hub delivering 1.45 V to GPU core, 1.8 V to memory interface, 2.8 V to I/O, and 3.3 V to display driver - all with synchronized startup. Use Value: Reduces board area vs discrete regulators; eliminates external sequencing logic; enables dynamic GPU voltage scaling during gameplay to extend battery life. |
Use Scenario: High-fidelity portable media players with HDD, DAC, headphone amplifier, and touch UI. IC Role / Device Role / Timing Role: Low-noise power source for analog audio chain (LDO2), digital logic (LDO1), HDD motor (buck-boost), and system MCU (Buck2). Use Value: LDO2's 50 µVRMS noise ensures clean DAC reference; buck-boost maintains 3.3 V during battery sag; STAT/CHG pins drive status LEDs without external drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Three buck converters + two LDOs; no buck-boost; no integrated Li-ion charger; 400-kHz I²C; 48-pin QFN | Lacks battery charging and wide-input buck-boost; suited for non-battery systems or external charger designs | Choose when battery management is handled externally and buck-boost functionality is unnecessary |
| TPS65053RGER | Two bucks + three LDOs; no ADC; no battery charger; 400-kHz I²C; 24-pin VQFN | Smaller footprint but missing key LP3910SQ-AP/NOPB functions: battery telemetry, thermistor sensing, and multi-source charging | Select for simpler, lower-cost portable systems without battery health monitoring or dual-source charging requirements |
Compared with TPS65023RSBR and TPS65053RGER, the LP3910SQ-AP/NOPB uniquely integrates buck-boost regulation, linear battery charging with 0.35% VTERM accuracy, and 4-channel ADC-based battery supervision - making it the only option among the three suitable for HDD-based portable devices requiring autonomous battery-aware power sequencing.
Availability
LP3910SQ-AP/NOPB is available at Aetrix Electronics and suitable for hard drive-based media players, portable navigation devices, portable gaming players, and audio/video media players requiring stable component supply, long-lifecycle support, and consistent parametric performance across production batches.
Supply support for LP3910SQ-AP/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in portable and battery-powered system solutions.
The LP3910 product line was developed specifically for HDD-based portable media players, integrating power conversion, battery management, and system supervision into a single IC to reduce bill-of-materials and simplify PCB layout in space-constrained consumer electronics.
FAQ
What is the default output voltage configuration for LP3910SQ-AP/NOPB?
The LP3910SQ-AP/NOPB is factory-programmed with LDO1 = 2.8 V, LDO2 = 1.5 V, Buck1 = 1.45 V, Buck2 = 1.8 V, and Buck-Boost = 3.3 V. These defaults are defined in Table 2 of the SNVS481M datasheet and can be modified via I²C register writes after power-up. The LP3910SQ-AP/NOPB retains these settings until reprogrammed, enabling immediate operation without host initialization.
Does LP3910SQ-AP/NOPB support both USB and wall adapter charging simultaneously?
No - the LP3910SQ-AP/NOPB implements priority-based charging arbitration: wall adapter (CHG_DET) takes precedence over USB (USBPWR). When both sources are present, the device disables USB charging and draws from the adapter. This behavior is hardwired and cannot be overridden; the LP3910SQ-AP/NOPB does not support concurrent dual-source charging or power-path management.
How is battery temperature monitored on LP3910SQ-AP/NOPB?
The LP3910SQ-AP/NOPB monitors battery temperature via the TS pin, which connects to a 100-kΩ NTC thermistor in series with an internal 8-µA current source. The resulting voltage is digitized by the integrated 8-bit ADC. Thresholds for thermal regulation (e.g., 45°C/50°C) are set in the CHSPV register, and the LP3910SQ-AP/NOPB triggers thermal interrupts or reduces charge current if thresholds are exceeded.
What is the purpose of the IREF pin on LP3910SQ-AP/NOPB?
The IREF pin on LP3910SQ-AP/NOPB sets the internal bias current generator using an external 121-kΩ resistor to AGND. This resistor determines the reference current used across multiple internal circuits, including the ADC reference, LDO biasing, and charger current sensing. Deviation from 121 kΩ alters calibration accuracy; the LP3910SQ-AP/NOPB datasheet specifies ±1% tolerance for optimal performance.
Can LP3910SQ-AP/NOPB operate without an I²C host controller?
Yes - the LP3910SQ-AP/NOPB powers up with factory-default voltages and sequencing delays and operates autonomously. All rails regulate and the charger functions without I²C communication. However, dynamic voltage scaling, ADC readback, fault logging, and custom sequencing require I²C interaction; standalone operation is limited to the pre-programmed AP configuration and lacks runtime configurability.
LP3910SQ-AP/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Handheld/Mobile Devices
- Current - Supply:
- -
- Voltage - Supply:
- 2.5V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (6x6)
LP3910SQ-AP/NOPB FAQ
1.How can I place an order for LP3910SQ-AP/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3910SQ-AP/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3910SQ-AP/NOPB reliable?
The price and inventory of LP3910SQ-AP/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3910SQ-AP/NOPB is usually 5 days.
3.What payment methods are accepted for LP3910SQ-AP/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3910SQ-AP/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3910SQ-AP/NOPB?
LP3910SQ-AP/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3910SQ-AP/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3910SQ-AP/NOPB?
For technical support, including LP3910SQ-AP/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3910SQ-AP/NOPB requirements.
6.How does Aetrix verify that LP3910SQ-AP/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3910SQ-AP/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3910SQ-AP/NOPB meets industry standards.
7.What is the process for return or replacement of LP3910SQ-AP/NOPB?
All LP3910SQ-AP/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3910SQ-AP/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3910SQ-AP/NOPB part is unused and in its original packaging.
Return procedure for LP3910SQ-AP/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP3910SQ-AP/NOPB Tags

-
TPS2511DGNR
Texas Instruments

-
UTC2000/MG
Microchip Technology

-
TUSB320HAIRWBR
Texas Instruments

-
TPS61252DSGR
Texas Instruments

-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments

-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments

-
STUSB1600AQTR
STMicroelectronics

-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments

-
TPS65150PWPR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

