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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Texas Instruments LP3923TL-VI/NOPB

Name: LP3923TL-VI/NOPB
Brand: Texas Instruments
SKU: LP3923TL-VI/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: LP3923TL-VI/NOPB

Manufacturer:: Texas Instruments

Category:: Power Management - Specialized

Package:: 30-WFBGA

Datasheet:: LP3923TL-VI/NOPB.pdf

Description:: PMU+CHGR+8 LDO+1 BUCK 30USMD

Quantity:: RFQ Add To RFQ list

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Product details

Overview

LP3923TL-VI/NOPB from Texas Instruments is a fully integrated cellular phone power management unit (PMU) featuring one 700 mA synchronous buck regulator, eight low-noise LDOs (including two LILO-type), and a programmable Li-ion battery charger with 50–1200 mA current range, 28 V OVP, and thermal regulation - deployed in CDMA handset baseband processor power domains for memory, RF, and peripherals.

For engineers reviewing the LP3923TL-VI/NOPB datasheet, LP3923TL-VI/NOPB pinout, LP3923TL-VI/NOPB application, or LP3923TL-VI/NOPB equivalent, this device requires attention to I²C-compatible serial interface control, SEL pin configuration for LDO1/LDO2 supply routing (VBATT vs. buck output), thermal shutdown alarm timing, and external feedback resistor selection for buck output voltage setting.

Technical Context

The LP3923TL-VI/NOPB integrates a high-efficiency synchronous buck regulator operating at 2 MHz with auto PFM/PWM mode switching and external FB divider-based output voltage programming (default 1.8 V). Its eight LDOs are partitioned into A-type (low-noise, 10 µV RMS, 75 dB PSRR), D-type (standard, 35 µV RMS), and LILO-type (low-input/low-output, configurable via SEL pin), each with independent enable controls (RX_EN, TX_EN, TCXO_EN, etc.) and 2% output voltage accuracy.

Charger functionality includes pre-charge, CC/CV, and maintenance modes with programmable termination voltage (4.1–4.4 V), restart threshold (50–200 mV below VTERM), and end-of-charge current (0.05C–0.2C); charging current is monitored via analog IMON output, and input overvoltage protection clamps up to +28 V on CHG_IN without external components.

Key Specifications

Parameter	Value and Actual Design Meaning
Buck Output Current	700 mA typical; supports digital core loads when LDO1/LDO2 are supplied from VBATT instead of buck output.
LDO Count & Types	8 total: 2 LILO (LDO1/LDO2), 4 A-type (LDO4–LDO7), 2 D-type (LDO3/LDO8); enables mixed-noise-domain power delivery.
Charging Current Range	50–1200 mA in 50 mA steps; allows precise adaptation to battery capacity and thermal constraints.
Input Voltage Range	3.0–5.5 V for VBATT/VIN1/VIN2/VINB; CHG_IN accepts 4.5–6.8 V with 28 V absolute max OVP.
Output Voltage Accuracy	±2% typical across all LDOs; ensures stable rail integrity for sensitive RF and analog circuitry.
Digital Interface	I²C-compatible SDA/SCL; enables dynamic on/off control, voltage programming, and status readback during operation.
Package	30-bump, 3.0 × 2.5 mm DSBGA; supports high-density mobile PCB layouts with minimal footprint.

Pinout & Package

LP3923TL-VI/NOPB uses a 30-bump, 3.0 mm × 2.5 mm DSBGA package with 0.4 mm pitch and bottom-side ball layout. Thermal performance is characterized at θ_JA = 39°C/W on JEDEC-standard PCB.

Pin/Terminal	Circuit Role	Design Meaning
A1–A5, B1, B5, C1, C5, D1, E1, F5	LDO outputs (LDO4–LDO8, LDO2, LDO3, LDO1, SW, BATT)	Eight regulated voltage outputs plus buck switch node and main battery connection; each assigned fixed function per pin map.
A4, C1, F1, E5	Power inputs (VIN2, VIN1, VINB, CHG_IN)	Dedicated inputs for LDO banks, buck stage, and charger; isolation prevents cross-regulator noise coupling.
B2–B4, D2, D3, E2–E3, E4, F4	Digital control signals (TCXO_EN, RX_EN, TX_EN, SEL, PON_N, HF_PWR, PWR_ON, SCL, ACOK_N)	Enable, sequencing, and status pins with defined logic thresholds (V_IL = 0.25×V_LDO3, V_IH = 0.75×V_LDO3) and internal pull-downs where specified.
C4, F3	Analog monitor/feedback (IMON, FB)	IMON provides real-time charging current monitoring (voltage proportional to I_CHG); FB sets buck output via external resistor divider.
D4, D5, F2	Interface & ground (SDA, GND, GNDB)	Open-drain SDA requires external 1.5 kΩ pull-up; separate GNDB isolates buck power ground from signal ground.

Key Features

Feature	Design Value
Integrated Li-ion charger with power FET	Eliminates external MOSFET and reverse-blocking diode; reduces BOM count and board area in portable systems.
LILO LDO architecture (LDO1/LDO2)	Enables efficient low-voltage operation when powered from buck output (e.g., 1.8 V → 1.8 V), minimizing dropout loss and heat generation.
A-type LDOs with 10 µV RMS noise	Meets stringent RF section requirements (e.g., TCXO, RX/TX chains) by suppressing supply-induced phase noise and spurs.
Thermal regulation + early-warning shutdown	Prevents thermal runaway during high-current charging or heavy load transients; alarm allows host-controlled throttling before shutdown.
I²C programmability of all regulators	Permits dynamic power-state transitions (e.g., sleep/wake sequences) without hardware reconfiguration or reset cycles.

Applications

CDMA Handset Baseband Power	RF Front-End Biasing
Use Scenario: Powering baseband processor domains (CORE, FLASH, DIGI) with independent voltage and sequencing control in CDMA cellular handsets. IC Role / Device Role / Timing Role: Central PMU managing buck-derived core rails and LDO-supplied peripheral rails under I²C host coordination. Use Value: Reduces discrete component count by integrating charger, buck, and eight LDOs in one DSBGA package while supporting dynamic voltage scaling.	Use Scenario: Supplying ultra-low-noise bias to TCXO, RX, and TX modules requiring stable 3.0 V at ≤150 mA with <10 µV RMS ripple. IC Role / Device Role / Timing Role: A-type LDO4 (TCXO_EN-controlled), LDO5 (RX_EN), and LDO6 (TX_EN) deliver isolated, sequenced analog power. Use Value: 75 dB PSRR and 10 µV RMS noise prevent clock jitter and receiver desensitization in crowded RF environments.
Li-ion Battery Charging System	Multi-Rail Portable System Management
Use Scenario: Charging single-cell Li-ion batteries from USB or AC adapter inputs with thermal-aware current limiting and voltage termination. IC Role / Device Role / Timing Role: Integrated charger block with IMON monitoring, 28 V OVP, and programmable CV/CC thresholds. Use Value: Eliminates need for external OVP circuitry and enables accurate state-of-charge estimation via analog IMON output.	Use Scenario: Consolidating power delivery for memory, vibrator, GP, and peripheral devices in space-constrained handheld electronics. IC Role / Device Role / Timing Role: LDO7 (always-on 3.0 V), LDO8 (GP 3.0 V), and buck output (configurable 0.8–2.5 V) serve diverse subsystems. Use Value: Independent enable pins (e.g., TCXO_EN, RX_EN) allow fine-grained power gating to extend battery life between active states.

CDMA Handset Baseband Power

RF Front-End Biasing

Use Scenario: Powering baseband processor domains (CORE, FLASH, DIGI) with independent voltage and sequencing control in CDMA cellular handsets.

IC Role / Device Role / Timing Role: Central PMU managing buck-derived core rails and LDO-supplied peripheral rails under I²C host coordination.

Use Value: Reduces discrete component count by integrating charger, buck, and eight LDOs in one DSBGA package while supporting dynamic voltage scaling.

Use Scenario: Supplying ultra-low-noise bias to TCXO, RX, and TX modules requiring stable 3.0 V at ≤150 mA with <10 µV RMS ripple.

IC Role / Device Role / Timing Role: A-type LDO4 (TCXO_EN-controlled), LDO5 (RX_EN), and LDO6 (TX_EN) deliver isolated, sequenced analog power.

Use Value: 75 dB PSRR and 10 µV RMS noise prevent clock jitter and receiver desensitization in crowded RF environments.

Li-ion Battery Charging System

Multi-Rail Portable System Management

Use Scenario: Charging single-cell Li-ion batteries from USB or AC adapter inputs with thermal-aware current limiting and voltage termination.

IC Role / Device Role / Timing Role: Integrated charger block with IMON monitoring, 28 V OVP, and programmable CV/CC thresholds.

Use Value: Eliminates need for external OVP circuitry and enables accurate state-of-charge estimation via analog IMON output.

Use Scenario: Consolidating power delivery for memory, vibrator, GP, and peripheral devices in space-constrained handheld electronics.

IC Role / Device Role / Timing Role: LDO7 (always-on 3.0 V), LDO8 (GP 3.0 V), and buck output (configurable 0.8–2.5 V) serve diverse subsystems.

Use Value: Independent enable pins (e.g., TCXO_EN, RX_EN) allow fine-grained power gating to extend battery life between active states.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power management unit applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65023RSBR	Three buck + six LDOs; no integrated Li-ion charger; I²C interface; 48-pin QFN	Requires external charger IC; better suited for systems using external battery management or non-Li-ion chemistries	Select when charger integration is unnecessary and higher buck count is prioritized over compact DSBGA footprint
LP3971TL/NOPB	Single buck + five LDOs + Li-ion charger; lower LDO count (5 vs. 8); same DSBGA-30 package	Limited rail count restricts use in complex multi-domain handsets; lacks LILO LDO architecture	Choose for simpler designs needing fewer regulated outputs but retaining charger + buck integration in identical form factor

Compared with TPS65023RSBR and LP3971TL/NOPB, LP3923TL-VI/NOPB uniquely combines eight LDOs-including dual LILO types-with integrated charger and buck in a 3.0 × 2.5 mm DSBGA, making it optimal for CDMA handset PMU consolidation where space, noise, and battery charging are co-constrained.

Availability

LP3923TL-VI/NOPB is available at Aetrix Electronics and suitable for CDMA handset design, RF module power delivery, and portable Li-ion charging systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LP3923TL-VI/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in mobile power architecture.

The LP3923TL-VI/NOPB belongs to TI's Cellular PMU product line, engineered specifically for CDMA handset baseband power consolidation-integrating charger, buck, and multiple LDOs to minimize footprint and maximize battery runtime.

FAQ

What is the default output voltage configuration for LDO1 and LDO2 on the LP3923TL-VI/NOPB?

The LP3923TL-VI/NOPB configures LDO1 and LDO2 as LILO regulators with default 1.8 V output when SEL is tied to VBATT, and as standard 3.0 V outputs when SEL is grounded. This dual-mode behavior allows flexible power routing depending on whether the buck output or main battery supplies these rails - critical for optimizing efficiency in varying load conditions.

How does the LP3923TL-VI/NOPB handle overvoltage protection on its CHG_IN pin?

The LP3923TL-VI/NOPB incorporates an internal 28 V overvoltage protection (OVP) circuit on the CHG_IN pin, which clamps input transients without requiring external protection components. This feature safeguards the entire PMU during USB or AC adapter hot-plug events and eliminates the need for discrete TVS diodes or series FETs in the charging path.

Can the buck regulator on the LP3923TL-VI/NOPB be used simultaneously to power LDO1/LDO2 and external circuitry?

No - when the LP3923TL-VI/NOPB routes the buck output to supply LDO1 and LDO2 (SEL = VBATT), the buck's full 700 mA capacity is consumed internally and cannot drive external loads. To use the buck as a general-purpose power channel, configure SEL = GND so LDO1/LDO2 draw from VBATT, freeing the buck output for external digital loads at default 1.8 V.

What is the purpose of the IMON pin on the LP3923TL-VI/NOPB, and how is it calibrated?

The IMON pin on the LP3923TL-VI/NOPB provides an analog voltage output proportional to the instantaneous charging current (typically 1 V per 1 A). It enables real-time battery charge monitoring and state-of-charge estimation without external sense resistors - calibration is factory-trimmed, with ±5% accuracy over temperature, eliminating need for system-level compensation.

Does the LP3923TL-VI/NOPB support automatic power-up sequencing without external microcontroller intervention?

Yes - the LP3923TL-VI/NOPB implements autonomous power-up sequencing triggered by HF_PWR or PWR_ON assertion. Once enabled, it executes internal startup timing (e.g., 140 µs buck start-up, 35 µs LDO start-up), asserts PS_HOLD, and releases RESET_N after stable regulation - enabling "push-button" boot without host CPU involvement during cold start.

LP3923TL-VI/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 30-WFBGA

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Applications:: Cellular, CDMA Handset

Current - Supply:: -

Voltage - Supply:: 3V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 30-DSBGA

LP3923TL-VI/NOPB FAQ

1.How can I place an order for LP3923TL-VI/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for LP3923TL-VI/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LP3923TL-VI/NOPB reliable?

The price and inventory of LP3923TL-VI/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3923TL-VI/NOPB is usually 5 days.

3.What payment methods are accepted for LP3923TL-VI/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3923TL-VI/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LP3923TL-VI/NOPB?

LP3923TL-VI/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LP3923TL-VI/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LP3923TL-VI/NOPB?

For technical support, including LP3923TL-VI/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3923TL-VI/NOPB requirements.

6.How does Aetrix verify that LP3923TL-VI/NOPB is sourced from the original manufacturer or authorized distributors?

All LP3923TL-VI/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3923TL-VI/NOPB meets industry standards.

7.What is the process for return or replacement of LP3923TL-VI/NOPB?

All LP3923TL-VI/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3923TL-VI/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LP3923TL-VI/NOPB part is unused and in its original packaging.

Return procedure for LP3923TL-VI/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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