Analog Devices Inc. LT1161CN#PBF

Overview

LT1161CN#PBF from Analog Devices (formerly Linear Technology) is a quad protected high-side N-channel MOSFET driver IC designed for industrial, avionics, and automotive power switching. It features four independent channels, each with an integrated charge pump (750 kHz), individual short-circuit protection, programmable current limit (50–80 mV threshold), automatic restart timers, and flowthrough pinout. It operates from 8V to 48V supply and withstands –15V to 60V transients - enabling robust solenoid, motor, and circuit breaker control in harsh environments.

For engineers reviewing the LT1161CN#PBF datasheet, LT1161CN#PBF pinout, LT1161CN#PBF application, or LT1161CN#PBF equivalent, key selection criteria include its 20-lead PDIP package, TTL/CMOS-compatible inputs with 200 mV hysteresis, gate drive voltage up to 14 V above V+, 65 mV typical drain sense threshold with +0.33%/°C TC, and independent channel timing via external CT capacitors.

Technical Context

The LT1161CN#PBF implements a self-contained per-channel architecture: each of the four channels integrates a 750 kHz charge pump to generate gate voltage ~12 V above V+, a supply-referenced drain sense comparator (65 mV nominal threshold), and a timer circuit with 14 µA constant-current recharge. The device uses Kelvin-connected V+ pins (11, 20) as both supply and current-sense reference, requiring direct connection to the positive side of external sense resistors.

Channel enable logic requires both input voltage >2 V and timer voltage >3 V to activate gate drive; open inputs default low via internal 75 kΩ pull-downs, while timer pins float high via 14 µA pull-up. Fault response includes immediate gate turn-off (<50 µs), timer discharge, and automatic restart after CT recharges to 3 V - with trip delay adjustable via RD/CD networks for capacitive loads.

Key Specifications

Pinout & Package

LT1161CN#PBF is housed in a 20-lead plastic DIP (N package), 0.300" wide, with dual ground (pins 1, 10) and dual supply (pins 11, 20) for Kelvin sensing. Pin numbering follows standard top-view layout with pin 1 in bottom-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-side MOSFET driver applications.

Compared with LT1161CN#PBF, LT1910CS8#PBF offers simplified fault signaling but sacrifices channel count and timing flexibility, while TPS2H160-Q1 delivers automotive qualification and diagnostics at the cost of analog current threshold tunability and external timing capacitor control.

Availability

LT1161CN#PBF is available at Aetrix Electronics and suitable for industrial circuit breakers, avionics power distribution units, automotive solenoid control, and stepper motor phase drivers requiring stable component supply across extended temperature and transient-voltage conditions.

Supply support for LT1161CN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains full technical and manufacturing continuity for legacy Linear products including the LT1161 family.

The LT1161 product line was engineered specifically for high-reliability high-side switching in electrically noisy, transient-heavy environments - targeting industrial control, aerospace, and automotive applications where discrete protection and predictable fault recovery are critical.

FAQ

What is the maximum gate drive voltage capability of the LT1161CN#PBF relative to V+?

The LT1161CN#PBF delivers a gate drive voltage up to 14 V above the V+ supply rail - for example, 38 V when V+ = 24 V. This voltage-limited pumping ensures safe operation with N-channel MOSFETs rated for ≥15 V VGS, preventing gate oxide overstress. The actual value depends on V+: it is 4–6 V above V+ at 8 V, rising to 10–14 V above V+ at 24–48 V, as confirmed in the Electrical Characteristics table (VGATE – V+ parameter).

How does the LT1161CN#PBF implement individual short-circuit protection per channel?

The LT1161CN#PBF uses a per-channel drain sense comparator referenced to V+. When the voltage at a DSx pin drops more than 50–80 mV (typ. 65 mV) below V+, the corresponding gate is turned off within 25–50 µs. Simultaneously, the associated timer pin is discharged, initiating an automatic restart cycle timed by an external CT capacitor. Each channel operates independently - a fault on channel 1 does not affect channels 2–4.

Can the LT1161CN#PBF be used with low-side MOSFET configurations?

Yes - although designed for high-side switching, the LT1161CN#PBF can drive low-side N-MOSFETs by adding a Zener clamp (e.g., 1N4744) from gate to source to limit VGS. The gate drive current is internally limited, eliminating need for series resistance. Current sensing requires either returning the load to V+ (if within LT1161 supply range) or using external circuitry (e.g., op-amp level shift) to interface source-sense voltage to the DSx pin.

What is the purpose of the dual V+ pins (11 and 20) on the LT1161CN#PBF?

The dual V+ pins (11 and 20) on the LT1161CN#PBF serve two critical roles: first, they provide parallel power supply connections to reduce impedance and improve current handling; second, and more importantly, they act as Kelvin sense points for the internal drain sense comparators - requiring direct connection to the positive side of each external sense resistor to maintain accuracy. Both pins must be externally tied together and to the same node.

Does the LT1161CN#PBF require specific input/supply sequencing during power-up?

No - the LT1161CN#PBF has no input/supply sequencing requirements. Inputs are valid from 0 V to 15 V regardless of V+ state, and the device tolerates V+ ramping after input assertion. If V+ is applied while inputs are high, gate turn-on is delayed until the internal timer capacitor charges to 3 V (i.e., one full restart cycle), ensuring controlled startup without shoot-through risk.