Analog Devices Inc. LTC1156CSW#PBF

Overview

LTC1156CSW#PBF from Analog Devices (formerly Linear Technology) is a quad high-side micropower MOSFET driver with integrated charge pump, designed to fully enhance N-channel power MOSFETs in high-side switching applications. It operates from 4.5V to 18V, draws only 16µA standby current and 95µA per channel ON current, and provides gate drive up to VS + 25V at 12V supply - enabling efficient laptop power management and battery-powered systems.

For engineers reviewing the LTC1156CSW#PBF datasheet, LTC1156CSW#PBF pinout, LTC1156CSW#PBF application, or LTC1156CSW#PBF equivalent, key selection criteria include internal charge pump operation, independent drain-sense overcurrent protection with programmable delay, TTL/CMOS-compatible inputs, controlled turn-on/off timing, and compatibility with low-R_DS(on) N-channel FETs in space-constrained 16-pin SOL packages.

Technical Context

The LTC1156CSW#PBF integrates four independent high-side drivers, each featuring adaptive charge pump circuitry that generates gate voltage above VS without external capacitors. Its analog section includes a precision 100mV current-sense comparator with ±0.1µA input bias and hysteresis-enabled TTL-to-CMOS input logic with 1.3V threshold.

Each channel supports independent overcurrent detection via DSx pins referenced to an on-chip 100mV reference, with fast short-circuit turn-off (5–16µs) and user-configurable RC delay to suppress false triggering during inrush. The device uses dual VS and dual GND pins for accurate sense-path routing and noise isolation between analog and digital blocks.

Key Specifications

Pinout & Package

Package: 16-pin Plastic SOL (Small Outline Leaded), 0.300" body width, surface-mount compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-side gate driver applications.

Compared with TPS2814DR and MAX14914ATP+, the LTC1156CSW#PBF uniquely combines quad integration, internal charge pump, 16µA standby, and analog current sense in a 16-pin SOL package - making it optimal for space- and power-constrained portable electronics where discrete component count must be minimized.

Availability

LTC1156CSW#PBF is available at Aetrix Electronics and suitable for laptop power management, SCSI termination, cellular telephone subsystem control, and low-frequency motor drive applications requiring stable component supply, long-lifecycle availability, and consistent parametric performance.

Supply support for LTC1156CSW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management ICs, serving precision instrumentation, communications, and industrial markets.

The LTC1156 product line was developed by Linear Technology specifically for micropower, high-side N-channel MOSFET control in battery-powered computing and portable electronics - emphasizing ultra-low quiescent current, integrated charge pumping, and robust fault protection.

FAQ

What is the maximum gate drive voltage achievable with the LTC1156CSW#PBF?

The LTC1156CSW#PBF generates gate voltage up to VS + 25V at 12V supply, VS + 9.0V at 5V supply, and VS + 15.0V at 6V supply. These values are specified in the Electrical Characteristics table under "VGATE – VS" and reflect the internal charge pump's output capability into typical gate capacitance loads. This ensures full enhancement of standard N-channel MOSFETs across its operating range.

Does the LTC1156CSW#PBF require external components for charge pump operation?

No, the LTC1156CSW#PBF does not require external charge pump components. Its internal adaptive charge pump includes on-die capacitors and oscillator circuitry, eliminating the need for external flying capacitors or diodes. This is explicitly stated in the Features list ("No External Charge Pump Components") and confirmed in the Applications section and Block Diagram description.

How is overcurrent protection implemented on the LTC1156CSW#PBF?

The LTC1156CSW#PBF implements overcurrent protection via four independent drain-sense inputs (DS1–DS4), each comparing the voltage drop across an external sense resistor to an internal 100mV reference. When exceeded, the corresponding gate is rapidly discharged. An external RC network can be added to the DS pin to introduce delay and prevent false triggering on inrush currents - a capability verified in the Typical Performance Characteristics and Applications diagrams.

What are the required connections for the dual VS and dual GND pins on the LTC1156CSW#PBF?

Per the datasheet Notes 1 and 5, both VS pins (3 and 8) must be connected together externally, and both GND pins (1 and 6) must also be connected together. Additionally, the VS connection should tie to the "top" of the sense resistor to maintain accurate current measurement - a requirement critical for proper operation of the internal 100mV comparator and confirmed in the Absolute Maximum Ratings and Applications sections.

Is the LTC1156CSW#PBF compatible with 3.3V logic inputs?

Yes, the LTC1156CSW#PBF is compatible with 3.3V logic inputs. Its input threshold is specified at 1.3V with ~100mV hysteresis, and VINH (input high voltage) is guaranteed ≥2.0V, while VINL (input low voltage) is ≤0.8V. A 3.3V CMOS signal therefore exceeds VINH by >1.3V margin and falls well within the valid logic-high range, as confirmed in the Electrical Characteristics table and Applications section.