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Analog Devices Inc. LTC3625EDE#PBF
- Part No.:
- LTC3625EDE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Power Management - Specialized
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LTC3625EDE#PBF.pdf
- Description:
- IC SUPERCAP CHARGER 1A 12DFN
- Quantity:
- Payment:
- Shipping:
Inventory:138
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Product details
Overview
LTC3625EDE#PBF from Analog Devices (formerly Linear Technology) is a 1A dual-cell supercapacitor charger IC that regulates two series-connected supercapacitors to 4.8V or 5.3V with automatic cell balancing, programmable buck charge current up to 1.1A, 2.7V–5.5V input range, and 23µA no-load quiescent current - deployed in server backup power and solid-state storage systems.
For engineers reviewing the LTC3625EDE#PBF datasheet, LTC3625EDE#PBF pinout, LTC3625EDE#PBF application, or LTC3625EDE#PBF equivalent, key selection criteria include per-cell voltage regulation (2.45V/2.70V), single/dual inductor mode control via CTL pin, PROG-resistor-programmed charge current, and shutdown current <1µA from both VIN and VOUT.
Technical Context
The LTC3625EDE#PBF integrates synchronous buck and boost regulators sharing VMID as a common node: the buck regulates current into CBOT (bottom capacitor) while the boost regulates current into CTOP (top capacitor), enabling active balancing without external resistors. Its dual-regulator topology dynamically alternates or concurrently operates both converters depending on CTL state and voltage conditions across VMID and VOUT.
Charge termination is determined by VOUT reaching 4.8V or 5.3V (set by VSEL), with 135mV recharge hysteresis and automatic sleep entry when regulation is achieved. The PROG pin servos to 1.2V and programs average buck current via IBUCK = (1.2V × 118,000)/RPROG, while the boost delivers fixed 2A typical input current with peak/valley limits of 2.12A/1.88A.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 5.5V - supports single-cell Li-ion, USB, or regulated 3.3V/5V rails without external LDO. |
| Output Regulation Options | 4.8V (2.45V/cell) or 5.3V (2.70V/cell) - selected by logic level on VSEL pin; enables compatibility with common supercapacitor voltage ratings. |
| Programmable Buck Charge Current | Up to 1.1A (RPROG = 71.5kΩ) - sets charging rate for bottom capacitor; determines total stack charge time in single/dual inductor modes. |
| Boost Input Current | 2A typical - fixed average input current into boost stage; delivers top-capacitor charge independent of buck current setting. |
| Quiescent Current (No Load) | 23µA at VIN = 3.6V - minimizes self-discharge impact during long-term backup operation. |
| Shutdown Current | <1µA from both VIN and VOUT - preserves stored energy when EN = low, critical for maintenance-free backup systems. |
| Operating Junction Temp | –40°C to 125°C - qualified for industrial and enterprise storage environments including RAID controllers and SSDs. |
Pinout & Package
The LTC3625EDE#PBF is housed in a 12-lead 3mm × 4mm × 0.75mm DFN package with exposed thermal pad (Pin 13) requiring solder connection to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1 (Pin 1) | Buck switch node | Connects external inductor to VMID; carries buck output current up to 1.1A average; PMOS/NMOS switching controlled internally. |
| VIN (Pin 2) | Main input supply | Accepts 2.7V–5.5V; requires ≥10µF ceramic bypass to GND; UVLO triggers at 2.63V/2.90V depending on VSEL state. |
| CTL (Pin 3) | Mode select input | Logic high = single-inductor operation (SW2 tied to SW1); logic low = dual-inductor operation; must be hard-tied, not floated. |
| VSEL (Pin 4) | Output voltage select | Logic low → 4.8V/4.0V sleep threshold; logic high → 5.3V/4.5V; internal 4.5MΩ pull-down active only when EN = high. |
| EN (Pin 5) | Enable input | Active-high logic; internal 4.5MΩ pull-down ensures default disable; drives device into sub-1µA shutdown when low. |
| PROG (Pin 6) | Charge current programming | Resistor to GND sets buck current; pin servos to 1.2V; clamps at 22.5µA if RPROG too low, limiting IBUCK to 2.65A. |
| PFI (Pin 7) | Power-fail input | High-impedance comparator input; monitors VIN via external divider; trips PFO when voltage drops below 1.2V (±15mV hysteresis). |
| PFO (Pin 8) | Power-fail open-drain output | Active-low signal indicating VIN undervoltage; requires external pull-up; remains low during shutdown or UVLO. |
| PGOOD (Pin 9) | Regulation status output | Open-drain flag asserting when VOUT reaches 92.5% of target; deasserts if VOUT falls below 89.5%; pulled low in shutdown. |
| VMID (Pin 10) | Capacitor stack midpoint | Monitored node between CTOP and CBOT; used to enable/disable buck/boost stages and enforce cell balancing; must connect to physical mid-node. |
| VOUT (Pin 11) | Stack output voltage | Connects to positive terminal of top supercapacitor; regulated to 4.8V or 5.3V; sleep mode activates when target reached + hysteresis. |
| SW2 (Pin 12) | Boost switch node | Connects external inductor to VMID; carries boost input current up to 2A average; tied to SW1 in single-inductor mode. |
| GND (Pin 13) | Ground / thermal pad | Exposed pad; must be soldered to continuous PCB ground plane for thermal performance (θJA = 43°C/W) and electrical reference. |
Key Features
| Feature | Design Value |
|---|---|
| Automatic cell balancing | Eliminates need for passive balancing resistors by independently regulating CTOP and CBOT via dual buck/boost topology. |
| Single/dual inductor configuration | CTL pin selects operation mode: single inductor reduces BOM count; dual inductor cuts charge time nearly in half with concurrent converter operation. |
| Low-quiescent-current sleep mode | Draws only 23µA from VIN at no load and <1µA from VOUT in shutdown - extends supercapacitor hold-up time significantly. |
| Programmable per-cell voltage limit | VSEL pin selects 2.45V/2.70V per cell (LTC3625) - prevents overvoltage stress on mismatched or aging supercapacitors. |
| Integrated power-fail detection | PFI/PFO pins provide user-configurable input undervoltage warning without external comparators or reference circuits. |
Applications
| Server Backup Power | Solid-State Storage |
|---|---|
|
Use Scenario: Maintaining volatile cache or DRAM state during AC power loss in enterprise servers and RAID controllers. IC Role / Device Role / Timing Role: Supercapacitor charger and balancer ensuring rapid, safe recharging of 2×50F–100F stacks after power restoration. Use Value: Enables >72-hour hold-up with 2.7V–5.5V input compatibility and 23µA sleep current - eliminating battery replacement cycles. |
Use Scenario: Providing instant power to NAND flash write buffers and controller SRAM during unexpected power interruption in SSDs. IC Role / Device Role / Timing Role: Dual-regulator charger delivering precise 4.8V/5.3V stack voltage with <135mV recharge hysteresis for reliable data flush. Use Value: Prevents data corruption by guaranteeing ≥500ms of clean power delivery even with 20% capacitor aging or mismatch. |
| Wireless Smart Meters | Peak Power Boost Supplies |
|
Use Scenario: Supporting real-time clock and secure memory retention during grid outages in AMI meters with limited board space. IC Role / Device Role / Timing Role: Low-profile supercapacitor charger operating from 3.3V microcontroller rail with minimal external components (1 inductor, 1 resistor, 1 cap). Use Value: Achieves full stack charge in <90 seconds (RPROG = 71.5kΩ, dual inductor) while consuming only 23µA between wake events. |
Use Scenario: Delivering short-duration, high-current bursts (e.g., 2A for 100ms) to RF power amplifiers or motor drivers beyond source capability. IC Role / Device Role / Timing Role: Bidirectional-capable charger managing supercapacitor discharge into load and subsequent reconditioning via balanced dual-cell topology. Use Value: Sustains 3.5W peak loads for >200ms using 10F/10F stack, with automatic rebalancing preventing premature cell failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supercapacitor charging applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3625EDE-1#PBF | Fixed 4.0V/4.5V output options (2.05V/2.30V per cell) - lower per-cell voltage ceiling than LTC3625EDE#PBF's 2.45V/2.70V. | Targeted at lower-voltage-rated supercapacitors (e.g., 2.5V or 2.7V cells); unsuitable where 2.7V/cell tolerance is required. | Select LTC3625EDE-1#PBF only when system-level voltage margin permits reduced per-cell regulation; not drop-in compatible due to different VSEL mapping. |
| MAX17599ATP+T | Single-output 2-cell charger with fixed 5.4V output, no programmable current, no automatic balancing - relies on external resistive balancing network. | Lacks integrated cell balancing; requires ≥2% matching tolerance between capacitors; higher BOM count and lower efficiency in mismatched stacks. | Choose MAX17599ATP+T only for cost-sensitive, matched-capacitor designs where balancing overhead is acceptable; not functionally equivalent. |
Compared with LTC3625EDE-1#PBF and MAX17599ATP+T, the LTC3625EDE#PBF uniquely delivers programmable per-cell voltage limits, resistor-set charge current, and true active balancing - enabling robust operation with >2:1 capacitance mismatch and extending supercapacitor lifetime in mission-critical backup systems.
Availability
LTC3625EDE#PBF is available at Aetrix Electronics and suitable for server backup power, solid-state storage, and wireless metering applications requiring stable component supply, extended temperature operation (–40°C to 125°C), and long-term lifecycle support.
Supply support for LTC3625EDE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision analog and power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3625EDE#PBF belongs to Linear's supercapacitor charger product line, engineered specifically for high-reliability, zero-maintenance backup power in data infrastructure - emphasizing automatic cell balancing, ultra-low quiescent current, and seamless integration into compact storage and server platforms.
FAQ
What is the maximum supercapacitor voltage imbalance the LTC3625EDE#PBF can correct during charging?
The LTC3625EDE#PBF actively balances two series supercapacitors by independently regulating CTOP and CBOT via separate buck and boost stages. It tolerates up to 180mV offset after charging when CTL = 0V and up to 120mV when CTL = VIN, as verified in Electrical Characteristics tables. This correction occurs without external resistors and sustains balance even with severe initial mismatches like 50F/100F stacks shown in Typical Application TA01b.
How does the CTL pin affect charge time and efficiency in the LTC3625EDE#PBF?
The CTL pin configures the LTC3625EDE#PBF for single-inductor (CTL = high) or dual-inductor (CTL = low) operation. In dual mode, buck and boost converters run concurrently, reducing full-stack charge time by ~45% versus single mode at identical RPROG. Efficiency remains >85% in both modes, but dual mode increases peak inductor current handling requirements and adds one external inductor.
Can the LTC3625EDE#PBF operate with only one supercapacitor, or does it require two in series?
The LTC3625EDE#PBF requires two supercapacitors connected in series with VMID tapped at their junction - it cannot operate with a single capacitor. Its architecture depends on measuring VMID relative to VOUT to determine which cell needs charging, and the internal buck/boost regulators are topologically bound to this 2-cell configuration. Attempting single-capacitor use will result in undefined regulation behavior and potential overvoltage.
What happens to the LTC3625EDE#PBF when input voltage drops below UVLO during charging?
When VIN drops below the UVLO threshold (2.63V or 2.90V depending on VSEL), the LTC3625EDE#PBF disables both buck and boost regulators, enters low-power monitoring mode drawing ≤35µA from VIN, and pulls PGOOD and PFO low. Once VIN recovers above the rising threshold plus 100mV hysteresis, charging resumes automatically from the last known VMID/VOUT state without reset or reinitialization.
Is the PROG pin on the LTC3625EDE#PBF compatible with standard resistor values, and what is the minimum usable RPROG?
Yes - the PROG pin accepts standard E96-series resistors. With IBUCK = (1.2V × 118,000)/RPROG, RPROG = 61.9kΩ yields 2.3A (clamped), 71.5kΩ yields 1.98A (clamped), and 143kΩ yields 0.99A typical. The minimum functional RPROG is 0Ω (grounded), which clamps PROG current at 22.5µA and sets IBUCK to 2.65A - verified in Electrical Characteristics Note 5.
LTC3625EDE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Supercapacitor Charger
- Current - Supply:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DFN (4x3)
LTC3625EDE#PBF FAQ
1.How can I place an order for LTC3625EDE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3625EDE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3625EDE#PBF reliable?
The price and inventory of LTC3625EDE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3625EDE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3625EDE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3625EDE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3625EDE#PBF?
LTC3625EDE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3625EDE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3625EDE#PBF?
For technical support, including LTC3625EDE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3625EDE#PBF requirements.
6.How does Aetrix verify that LTC3625EDE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3625EDE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3625EDE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3625EDE#PBF?
All LTC3625EDE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3625EDE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3625EDE#PBF part is unused and in its original packaging.
Return procedure for LTC3625EDE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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