Analog Devices Inc. LTC3625IDE-1#PBF
- Part No.:
- LTC3625IDE-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Power Management - Specialized
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LTC3625IDE-1#PBF.pdf
- Description:
- IC SUPERCAP CHARGER 1A 12DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3625IDE-1#PBF from Analog Devices (formerly Linear Technology) is a 1A dual-cell supercapacitor charger IC designed to safely charge two series-connected supercapacitors with automatic cell balancing. It operates from 2.7V–5.5V input, delivers up to 4.5V output (2.25V per cell), supports single- or dual-inductor configurations, and draws only 8µA quiescent current at 3.6V input - ideal for solid-state hard drives and wireless power meters requiring reliable backup energy storage.
For engineers reviewing the LTC3625IDE-1#PBF datasheet, LTC3625IDE-1#PBF pinout, LTC3625IDE-1#PBF application, or LTC3625IDE-1#PBF equivalent, key selection criteria include per-cell voltage regulation (2.05V/2.25V), programmable buck charge current (up to 2.2A), shutdown current (<1µA), VMID-based balancing logic, and DFN-12 package compatibility with high-density PCB layouts.
Technical Context
The LTC3625IDE-1#PBF integrates a synchronous buck regulator (VIN→VMID) and a synchronous boost regulator (VMID→VOUT) to independently regulate voltage across bottom and top supercapacitors. Its dual-regulator topology enables real-time balancing without external resistors by dynamically enabling/disabling each converter based on VMID and VOUT feedback.
Charge mode is selected via CTL pin (GND = dual inductor, VIN = single inductor), while VSEL sets output voltage: low = 4.0V (2.05V/cell), high = 4.5V (2.25V/cell). PROG pin programs buck current using IBUCK = (1.2V × 118,000)/RPROG, and PGOOD asserts when VOUT reaches 92.5% of target with 3% hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 5.5V - supports single-cell Li-ion, USB, or regulated 3.3V/5V rails without external LDO. |
| Output Voltage (VSEL = 0) | 4.0V ±0.1V - fixed termination voltage enabling 2.05V/cell regulation to prevent overvoltage in mismatched stacks. |
| Buck Charge Current | Up to 2.20A (RPROG = 71.5kΩ) - programmable via single resistor; clamped at 2.65A during fault conditions. |
| Quiescent Current | 8µA at 3.6V input - enables multi-year battery-backed operation in low-power metering applications. |
| Shutdown Current | <1µA from both VIN and VOUT - eliminates leakage path between input supply and charged supercapacitors. |
| Operating Temp Range | –40°C to +125°C - qualified for industrial RAID systems and server backup modules exposed to thermal cycling. |
| Package | 12-lead 3mm × 4mm × 0.75mm DFN - exposes thermal pad (Pin 13) for direct PCB ground connection and 43°C/W θJA. |
Pinout & Package
Package: 12-lead (4mm × 3mm) plastic DFN with exposed thermal pad (Pin 13 = GND), rated for –40°C to +125°C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1 (Pin 1) | Buck switch node | Connects external inductor to VMID; internal PMOS/NMOS switches regulate CBOT current. |
| VIN (Pin 2) | Input power supply | Accepts 2.7V–5.5V; requires ≥10µF ceramic bypass capacitor to GND for stability. |
| CTL (Pin 3) | Charge mode control | Logic low = dual-inductor mode (faster charging); must be hard-tied to GND or VIN - no floating allowed. |
| VSEL (Pin 4) | Output voltage select | Logic low selects 4.0V/2.05V per cell; internal 4.5MΩ pull-down active only when EN = high. |
| EN (Pin 5) | Enable input | Active-high logic; 4.5MΩ internal pull-down ensures safe default-off state during power-up. |
| PROG (Pin 6) | Current programming | Servos to 1.2V; RPROG to GND sets IBUCK = (1.2V × 118,000)/RPROG; clamps at 22.5µA if shorted. |
| PFI (Pin 7) | Power-fail input | High-impedance comparator input (1.2V threshold); connects to resistor divider from VIN for custom UVLO. |
| PFO (Pin 8) | Power-fail output | Open-drain alert signal; pulled low when PFI < 1.2V - requires external pull-up for microcontroller interface. |
| PGOOD (Pin 9) | Output status indicator | Open-drain flag asserting when VOUT ≥92.5% of target; pulled low during UVLO or shutdown. |
| VMID (Pin 10) | Capacitor stack midpoint | Monitored node between CTOP and CBOT; used with VOUT to enable/disable buck/boost converters for balancing. |
| VOUT (Pin 11) | Stack output voltage | Connects to top supercapacitor anode; regulated to 4.0V (VSEL=0); feedback path for boost loop. |
| SW2 (Pin 12) | Boost switch node | Connects external inductor to VMID; tied to SW1 in single-inductor mode. |
| GND (Pin 13) | Ground reference | Exposed thermal pad - must be soldered to continuous PCB ground plane for thermal and electrical integrity. |
Key Features
| Feature | Design Value |
|---|---|
| Automatic cell balancing | Eliminates need for balancing resistors by dynamically controlling buck/boost regulators based on VMID and VOUT - prevents overvoltage even with 2:1 capacitance mismatch. |
| Dual-inductor fast-charge mode | CTL = GND enables simultaneous buck and boost operation, reducing full-stack charge time by ~50% versus single-inductor configuration. |
| Low-noise synchronous switching | Integrated 120mΩ PMOS and 100mΩ NMOS switches minimize conduction loss and EMI in compact layouts. |
| Intelligent sleep management | Enters sub-1µA shutdown when EN = low, and auto-wakes when VOUT drops >135mV below regulation - extends supercapacitor hold-up time. |
| Robust protection suite | Includes undervoltage lockout (2.63V rising threshold), overtemperature shutdown, reverse-current blocking, and clamped PROG current during faults. |
Applications
| Solid-State Hard Drives | Wireless Power Meters |
|---|---|
|
Use Scenario: Backup power for DRAM cache and firmware write operations during unexpected AC loss. IC Role / Device Role / Timing Role: Supercapacitor charger maintaining 4.0V stack voltage with precise 2.05V/cell regulation to ensure long-term capacitor reliability. Use Value: Enables >100,000 write cycles without electrolytic degradation - critical for industrial SSDs operating at 85°C ambient. |
Use Scenario: Energy harvesting buffer for NB-IoT cellular transmission bursts in utility metering. IC Role / Device Role / Timing Role: High-efficiency (≥85%) dual-regulator charger delivering 1A peak current to recharge 10F–100F supercapacitor stacks from intermittent solar input. Use Value: Achieves full recharge in <60 seconds (dual-inductor mode) while consuming only 8µA quiescent current between transmissions. |
| RAID Controller Backup | Server Hot-Swap Modules |
|
Use Scenario: Maintaining cache coherency during drive replacement or power failover in enterprise storage arrays. IC Role / Device Role / Timing Role: Automatic balancing IC preventing overvoltage on aged supercapacitors with >20% capacitance drift across 5-year service life. Use Value: Eliminates field failures caused by unbalanced discharge - validated for continuous operation at 125°C junction temperature. |
Use Scenario: Providing hold-up power for FPGA configuration and telemetry during hot-swap insertion/removal in modular servers. IC Role / Device Role / Timing Role: Low-profile DFN-packaged charger enabling <1.5mm board height while supporting 4.0V/4.5V selectable outputs via VSEL pin. Use Value: Reduces PCB area by 40% versus discrete solutions while meeting IPC-2221 creepage requirements for 5.5V input isolation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supercapacitor charging applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3625IDE#PBF | Supports higher 4.8V/5.3V output (2.45V/2.7V per cell); identical pinout, package, and feature set. | Required where legacy 2.5V-rated supercapacitors or higher-energy-density cells are used. | Select LTC3625IDE#PBF when system design mandates 4.8V stack voltage; otherwise LTC3625IDE-1#PBF provides tighter margin for 2.2V-rated cells. |
| MAX17222ETA+T | Single-cell 2.5V–5.5V charger with 500mA max current; no VMID monitoring or automatic balancing circuitry. | Lacks dual-regulator topology - requires external balancing resistors or matched capacitors. | Use MAX17222ETA+T only in cost-sensitive, low-current (<500mA), matched-capacitor designs where balancing overhead is acceptable. |
Compared with LTC3625IDE#PBF, the LTC3625IDE-1#PBF offers lower per-cell voltage (2.05V vs 2.45V) for enhanced safety margin with modern 2.2V-rated supercapacitors, while MAX17222ETA+T lacks integrated balancing - making LTC3625IDE-1#PBF the only drop-in solution for mismatch-tolerant, high-current dual-cell backup systems.
Availability
LTC3625IDE-1#PBF is available at Aetrix Electronics and suitable for solid-state hard drives, wireless power meters, and RAID controller backup systems requiring stable component supply across extended product lifecycles.
Supply support for LTC3625IDE-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors with deep expertise in precision power conversion and energy storage solutions.
The LTC3625IDE-1#PBF belongs to Linear's supercapacitor charger product line, engineered specifically for high-reliability backup power in industrial storage and metering applications where cell mismatch tolerance and ultra-low quiescent current are mandatory.
FAQ
What is the maximum supercapacitor voltage per cell supported by the LTC3625IDE-1#PBF?
The LTC3625IDE-1#PBF supports a maximum of 2.25V per cell when VSEL = high (5.3V total), but its default configuration with VSEL = low regulates to 2.05V per cell (4.0V total). This lower threshold provides enhanced safety margin for 2.2V-rated supercapacitors and prevents premature aging due to overvoltage stress - confirmed in Electrical Characteristics Table on page 2 of the datasheet.
How does the LTC3625IDE-1#PBF achieve automatic cell balancing without external resistors?
The LTC3625IDE-1#PBF achieves automatic balancing using dual synchronous regulators: a buck converter controls voltage across the bottom capacitor (CBOT) by regulating current into VMID, while a boost converter controls voltage across the top capacitor (CTOP) by regulating current from VMID to VOUT. The IC continuously monitors VMID and VOUT to enable/disable each regulator - ensuring neither cell exceeds its programmed threshold, even with 2:1 capacitance mismatch.
Can the LTC3625IDE-1#PBF operate with only one external inductor?
Yes - the LTC3625IDE-1#PBF supports single-inductor operation when CTL is tied to VIN. In this mode, SW1 and SW2 are internally connected, allowing the same inductor to serve both buck and boost paths. However, charge time increases ~2× versus dual-inductor mode, and a minimum 25mA load on VIN is required to prevent backfeeding during boost phase - details are specified in the "Single Inductor Operation" section of the datasheet.
What is the shutdown current specification for the LTC3625IDE-1#PBF?
The LTC3625IDE-1#PBF draws less than 1µA from both VIN and VOUT when EN is pulled low. This ultra-low shutdown current prevents parasitic discharge of charged supercapacitors and enables multi-year hold-up time in battery-free backup systems - verified in the Electrical Characteristics table under "Input SD Current" and "VOUT SD Current" rows.
Is the LTC3625IDE-1#PBF pin-compatible with the LTC3625IDE#PBF?
Yes - the LTC3625IDE-1#PBF is fully pin-compatible with the LTC3625IDE#PBF, sharing identical DFN-12 package dimensions, pinout, and control interface. The only functional difference is the VSEL-selectable output voltage range: LTC3625IDE-1#PBF offers 4.0V/4.5V, while LTC3625IDE#PBF offers 4.8V/5.3V. No PCB redesign is needed when substituting between these variants.
LTC3625IDE-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Supercapacitor Charger
- Current - Supply:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DFN (4x3)
LTC3625IDE-1#PBF FAQ
1.How can I place an order for LTC3625IDE-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3625IDE-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3625IDE-1#PBF reliable?
The price and inventory of LTC3625IDE-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3625IDE-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC3625IDE-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3625IDE-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3625IDE-1#PBF?
LTC3625IDE-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3625IDE-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3625IDE-1#PBF?
For technical support, including LTC3625IDE-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3625IDE-1#PBF requirements.
6.How does Aetrix verify that LTC3625IDE-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3625IDE-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3625IDE-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC3625IDE-1#PBF?
All LTC3625IDE-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3625IDE-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3625IDE-1#PBF part is unused and in its original packaging.
Return procedure for LTC3625IDE-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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