Analog Devices Inc. LTC7060HMSE#PBF

Overview

LTC7060HMSE#PBF from Analog Devices is a 100V half-bridge gate driver IC for dual N-channel MOSFETs in high-noise industrial and automotive power converters. It features independent floating grounds (SW and BGRTN), 0.8Ω pull-down / 1.5Ω pull-up drivers, programmable dead-time via external resistor, adaptive shoot-through protection, and operates with VCC from 6V to 14V and gate supplies from 4V to 14V - enabling robust control of high-threshold MOSFETs in synchronous buck, LLC, and motor drive stages.

For engineers reviewing the LTC7060HMSE#PBF datasheet, LTC7060HMSE#PBF pinout, LTC7060HMSE#PBF application, or LTC7060HMSE#PBF equivalent, this page delivers verified technical context, exact pin functions, real-world timing behavior under varying R_DT, confirmed thermal limits (–40°C to 150°C junction), and validated alternatives for half-bridge gate driving where ±10V ground differential immunity and 100V input voltage tolerance are required.

Technical Context

The LTC7060HMSE#PBF implements a symmetric double-floating architecture: high-side driver (TG/BST/SW) and low-side driver (BG/BGVCC/BGRTN) each reference independent return paths, enabling ±10V ground potential difference tolerance between input logic (SGND) and power stages. Its three-state PWM input uses fixed VIH/VIL thresholds (e.g., VIH(TG) = 3.1V, VIL(BG) = 1.25V) with internal 48kΩ pull-up and 42kΩ pull-down to enforce High-Z state when undriven.

Dead-time is precisely set by an external resistor (R_DT) on the DT pin, yielding 32ns (R_DT = 0Ω) to 250ns (R_DT open), with linear scaling per 0.44 ns/kΩ. Adaptive shoot-through protection monitors gate-source voltage transitions to prevent simultaneous conduction - independent of programmed dead-time - while UVLO/OVLO circuitry disables outputs if VCC falls below 5.3V or rises above 14.6V, or if either floating supply (BST–SW or BGVCC–BGRTN) drops below 3.4V.

Key Specifications

Pinout & Package

Package: 12-lead plastic MSOP with exposed pad (Pin 13 = SGND), θ_JA = 40°C/W. Exposed pad must be soldered to PCB ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with LM5109BMM/NOPB and UCC27211DRCR, the LTC7060HMSE#PBF uniquely delivers programmable dead-time, true floating grounds with ±10V tolerance, and AEC-Q100 H-grade reliability - making it the only option among the three qualified for automotive 48V systems and industrial converters operating near 100V rails with ground noise.

Availability

LTC7060HMSE#PBF is available at Aetrix Electronics and suitable for automotive DC-DC converters, industrial motor drives, and telecom rectifiers requiring stable component supply across extended temperature and high-voltage stress conditions.

Supply support for LTC7060HMSE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and automotive markets.

The LTC7060HMSE#PBF belongs to Analog Devices' Power by Linear™ high-voltage gate driver family, engineered specifically for noise-immune, high-reliability half-bridge control in automotive and industrial power conversion where ground isolation and programmable timing are critical.

FAQ

What is the maximum allowable voltage difference between SGND and BGRTN or SW in the LTC7060HMSE#PBF?

The LTC7060HMSE#PBF supports up to ±10V voltage difference between SGND and either BGRTN or SW pins. This specification is explicitly stated in the Applications section and Absolute Maximum Ratings table, ensuring reliable operation in systems with significant ground potential shifts - such as automotive chassis-to-battery isolation or industrial multi-ground systems. The LTC7060HMSE#PBF maintains functional integrity within this range without latch-up or parameter drift.

How does the LTC7060HMSE#PBF implement adaptive shoot-through protection, and is it independent of the DT pin setting?

The LTC7060HMSE#PBF uses hardware-level monitoring of gate-source voltage transitions on the external MOSFETs to detect imminent shoot-through - disabling the opposing driver before cross-conduction occurs. This function operates independently of the DT pin resistor value and remains active even when DT is open-circuit (250ns dead-time). The LTC7060HMSE#PBF datasheet confirms this in the "Adaptive Shoot-Through Protection" section, distinguishing it from fixed-delay-only solutions.

Can the LTC7060HMSE#PBF drive both logic-level and standard-threshold MOSFETs, and what gate supply voltage range enables this?

Yes, the LTC7060HMSE#PBF supports gate supply voltages from 4V to 14V on both BST–SW and BGVCC–BGRTN rails, enabling direct drive of logic-level MOSFETs (requiring ≥4.5V V_GS) and standard-threshold devices (requiring ≥10V V_GS). This range is specified in the Electrical Characteristics table under V_BST-SW and V_VBGVCC-BGRTN. The LTC7060HMSE#PBF's 0.8Ω pull-down and 1.5Ω pull-up ensure sufficient peak current across this full range.

What thermal derating applies to the LTC7060HMSE#PBF at 150°C junction temperature?

The LTC7060HMSE#PBF is rated for continuous operation up to 150°C junction temperature (H-grade), but the datasheet notes that "high junction temperature degrades operation lifetimes; operating lifetime is derated for junction temperatures greater than 125°C." No specific derating curve is provided, so design margins should maintain T_J ≤ 125°C for long-term reliability. The LTC7060HMSE#PBF thermal shutdown activates at ~180°C, providing fail-safe protection beyond the rated limit.

Is the FLT pin on the LTC7060HMSE#PBF actively driven or open-drain, and what fault conditions trigger it?

The FLT pin on the LTC7060HMSE#PBF is an open-drain N-channel MOSFET output with 60Ω typical pull-down resistance. It asserts low during four confirmed fault conditions: V_CC UVLO (<5.3V) or OVLO (>14.6V), BST–SW UVLO (<3.4V), BGVCC–BGRTN UVLO (<3.4V), or junction temperature ≥180°C. After fault clearance, FLT releases after a fixed 100µs delay, as documented in the Fault Flag section of the datasheet. The LTC7060HMSE#PBF requires an external pull-up resistor (e.g., 51kΩ to V_CC) for proper logic-level signaling.