Analog Devices Inc. LTC7060JMSE#PBF
- Part No.:
- LTC7060JMSE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Gate Drivers
- Package:
- 12-TSSOP (0.118", 3.00mm Width) Exposed Pad
- Datasheet:
-
LTC7060JMSE#PBF.pdf
- Description:
- IC GATE DRVR HALF-BRIDGE 12MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC7060JMSE#PBF from Analog Devices is a 100V half-bridge gate driver IC for dual N-channel MOSFETs in high-noise industrial and automotive power converters, featuring independent floating grounds (±10V tolerance), programmable dead-time (32–250 ns), 0.8Ω pull-down / 1.5Ω pull-up drive strength, and adaptive shoot-through protection.
For engineers reviewing the LTC7060JMSE#PBF datasheet, LTC7060JMSE#PBF pinout, LTC7060JMSE#PBF application, or LTC7060JMSE#PBF equivalent, this page delivers verified functional identity, thermal-grade validation (–40°C to 150°C), floating supply UVLO thresholds (3.4V), three-state PWM interface behavior, and real-world dead-time tuning via external resistor - all critical for high-reliability half-bridge design.
Technical Context
The LTC7060JMSE#PBF implements a symmetric double-floating architecture: high-side driver (TG/BST/SW) and low-side driver (BG/BGVCC/BGRTN) operate with independent ground references, enabling robust operation under ±10V ground potential differences between input logic and power stages. Its level-shifting circuitry supports 100V maximum input voltage independent of VCC.
It integrates adaptive shoot-through protection that monitors gate-source voltages to prevent simultaneous conduction, plus programmable dead-time via DT pin (RDT = 0–100 kΩ yields 32–76 ns propagation delay). All drivers feature 4–14V floating supply range, 100 mA sink/source capability, and open-drain FLT fault flag with 60 Ω pull-down.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Max | 100V - Enables direct use in high-voltage DC/DC converters without level-shifting or auxiliary supplies. |
| VCC Range | 6V to 14V - Powers internal logic; includes 5.3V falling UVLO and 14.6V rising OVLO for stable bias control. |
| Floating Supply Range | 4V to 14V (BST–SW & BGVCC–BGRTN) - Supports logic-level and standard-threshold MOSFETs with adjustable gate drive strength. |
| Driver RDS(ON) | 0.8Ω pull-down / 1.5Ω pull-up - Delivers ~6A peak sink / ~3A peak source at 10V, enabling fast 3.3nF load switching (13–18 ns rise/fall). |
| Dead-Time Range | 32 ns to 250 ns - Programmable via single RDT resistor; ensures reliable shoot-through immunity across wide operating conditions. |
| Junction Temp Range | –40°C to 150°C - Validated J-grade rating enables deployment in under-hood automotive and high-temp industrial environments. |
| Shoot-Through Protection | Adaptive hardware-based - Monitors actual MOSFET VGS states to block cross-conduction, not just timing delays. |
Pinout & Package
Package: 12-lead plastic MSOP with exposed pad (Pin 13 = SGND), θJA = 40°C/W, thermally enhanced for high-power density layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PWM | Three-state logic input | Drives TG/BG complementary states; floats to High-Z (both outputs off) when undriven; internal 42kΩ pull-down / 48kΩ pull-up sets 2.1V threshold region. |
| EN | Enable control input | Logic-high (>1.2V) enables driver operation; internal 2MΩ pull-down ensures safe default-off state during startup or controller reset. |
| FLT | Open-drain fault indicator | Pulls to SGND on VCC UVLO/OVLO, floating supply UVLO, or thermal shutdown; 60Ω typical RPL, 100µs release delay. |
| DT | Dead-time programming node | Resistor-to-SGND sets BG→TG and TG→BG propagation delay (32–250 ns); no capacitor required. |
| TG | High-side gate driver output | Drives top N-MOSFET gate between BST and SW; 0.8Ω pull-down / 1.5Ω pull-up referenced to SW. |
| BG | Low-side gate driver output | Drives bottom N-MOSFET gate between BGVCC and BGRTN; identical drive strength and logic to TG. |
| BST | High-side floating supply input | Bootstrap supply for TG driver; must be ≥4V above SW; monitored for 3.4V UVLO relative to SW. |
| SW | High-side return / switch node | Kelvin-connected to top MOSFET source; withstands –10V to 100V vs SGND; reference for BST and TG. |
| BGVCC | Low-side floating supply input | Supply for BG driver; must be ≥4V above BGRTN; monitored for 3.4V UVLO relative to BGRTN. |
| BGRTN | Low-side return | Kelvin-connected to bottom MOSFET source; withstands –10V to 100V vs SGND; reference for BGVCC and BG. |
| VCC | IC bias supply | Powers internal logic and generates 4.5V rail; 5.3V UVLO ensures clean startup; independent of VIN and floating supplies. |
| SGND | Chip ground / thermal pad | Reference for VCC, EN, PWM, DT, FLT; exposed pad (Pin 13) must be soldered to PCB ground for electrical integrity and thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Symmetric floating architecture | Independent high-side (BST/SW) and low-side (BGVCC/BGRTN) grounds tolerate ±10V differential noise - eliminates need for isolated gate drivers in noisy systems. |
| Programmable dead-time | Single RDT resistor tunes propagation delay from 32 ns to 250 ns - enables precise optimization for MOSFET QG, layout parasitics, and switching frequency. |
| Adaptive shoot-through protection | Hardware-monitored VGS sequencing prevents simultaneous conduction - more reliable than fixed-delay schemes under voltage transients or temperature drift. |
| Three-state PWM interface | Internal resistor divider creates defined High-Z window (1.9–2.3V) - allows seamless DCM control and controller-initiated safe shutdown without external logic. |
| AEC-Q100 qualified (J-grade) | Validated for automotive under-hood operation up to 150°C junction - includes production-tested thermal shutdown (180°C trip) and lifetime derating guidance. |
Applications
| Automotive On-Board Charger (OBC) | Industrial Motor Drive Inverter |
|---|---|
|
Use Scenario: Half-bridge stage in bidirectional AC/DC converter for EV charging, operating at 100 kHz with 400–800V DC bus. IC Role / Device Role: Dual N-MOSFET gate driver with independent floating supplies, enabling direct connection to high-side and low-side switches without optocouplers or isolated supplies. Use Value: ±10V ground noise immunity prevents false triggering during regenerative braking transients; 150°C rating supports compact, sealed OBC enclosures. |
Use Scenario: 3-phase inverter driving 48V BLDC motor in factory automation, requiring robust EMI resilience and thermal margin. IC Role / Device Role: High-current gate driver per leg, leveraging 0.8Ω pull-down to rapidly discharge gate capacitance and suppress Miller-induced turn-on. Use Value: Adaptive shoot-through protection eliminates risk of shoot-through during rapid direction reversal; programmable dead-time accommodates varying MOSFET QG. |
| Telecom 48V Intermediate Bus Converter | Server PSU LLC Resonant Controller Interface |
|
Use Scenario: High-efficiency 48V-to-12V buck converter in telecom rectifier, switching at 300 kHz with tight regulation requirements. IC Role / Device Role: Gate driver for synchronous rectification stage, using three-state PWM to support discontinuous conduction mode (DCM) during light-load conditions. Use Value: Three-state input enables seamless transition into DCM without external logic; 4–14V floating supply range supports both logic-level and standard MOSFETs. |
Use Scenario: Driving half-bridge primary switches in resonant LLC topology, where precise dead-time control minimizes circulating current losses. IC Role / Device Role: Timing-critical gate driver with externally tuned dead-time (via RDT) to match resonant tank zero-voltage switching (ZVS) window. Use Value: Dead-time accuracy (±5 ns typical) ensures ZVS across line/load variations; 100V rating supports wide-input-range server PSUs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage half-bridge gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5109BMM/NOPB | Fixed 100 ns dead-time; no floating ground tolerance (max ±2V); 60V max VIN; no adaptive shoot-through protection. | Suitable only for lower-voltage, low-noise industrial SMPS; lacks AEC-Q100 qualification and thermal grade flexibility. | Select when cost sensitivity outweighs noise immunity and automotive compliance requirements. |
| UCC27211D | 120V max VIN; 1.8Ω/0.9Ω drive strength; no programmable dead-time; ±5V ground tolerance; no three-state PWM. | Better for ultra-high-voltage flyback or PFC stages; requires external logic for DCM control and dead-time adjustment. | Select when higher voltage margin is critical but floating ground noise immunity and integrated dead-time tuning are secondary. |
Compared with LM5109BMM/NOPB and UCC27211D, the LTC7060JMSE#PBF uniquely combines ±10V floating ground tolerance, adaptive shoot-through protection, and resistor-programmable dead-time in a single AEC-Q100-qualified package - making it the only option for automotive OBC and high-noise industrial inverters demanding guaranteed reliability without external timing components.
Availability
LTC7060JMSE#PBF is available at Aetrix Electronics and suitable for automotive on-board chargers, industrial motor drives, telecom intermediate bus converters, and server PSU resonant controllers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC7060JMSE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, automotive, and communications markets.
The LTC7060JMSE#PBF belongs to Analog Devices' Power by Linear™ high-voltage gate driver family, engineered specifically for noise-immune, thermally robust half-bridge control in automotive and industrial power conversion systems.
FAQ
What is the maximum allowable voltage difference between SGND and BGRTN or SW in the LTC7060JMSE#PBF?
The LTC7060JMSE#PBF supports up to ±10V ground potential difference between SGND and either BGRTN or SW. This specification is explicitly validated in the Absolute Maximum Ratings table and confirmed in the Applications section under "High Noise Immunity". Exceeding ±10V risks violating the –10V to 100V rating for BGRTN and SW pins relative to SGND, potentially causing latch-up or permanent damage. The device's symmetric floating architecture relies on this limit to maintain isolation integrity between logic and power domains.
How does the LTC7060JMSE#PBF implement adaptive shoot-through protection, and how is it different from fixed dead-time schemes?
The LTC7060JMSE#PBF uses hardware-monitored gate-source voltage sensing on both high-side and low-side MOSFETs to dynamically prevent simultaneous conduction - not just time-based blocking. Unlike fixed dead-time drivers, it verifies actual VGS states before enabling the opposing FET, eliminating shoot-through risk caused by layout parasitics, temperature drift, or MOSFET parameter variation. This is detailed in the "Adaptive Shoot-Through Protection" section of the datasheet and distinguishes the LTC7060JMSE#PBF from alternatives like UCC27211D or LM5109B.
What is the purpose of the NC pin (Pin 5) on the LTC7060JMSE#PBF, and why is it skipped in the pinout?
Pin 5 of the LTC7060JMSE#PBF is designated NC (No Internal Connection) and must remain unconnected. It is intentionally omitted from the functional pin sequence to provide physical isolation between adjacent high-voltage terminals - specifically between DT (Pin 4) and VCC (Pin 6) - reducing creepage/clearance risk in high-voltage PCB layouts. The datasheet explicitly states "Always keep this pin floating" and confirms no internal bond wire or circuit connection exists. Soldering or routing to Pin 5 violates the recommended layout guidelines.
Can the LTC7060JMSE#PBF drive both logic-level and standard-threshold MOSFETs, and what supply voltage range supports this?
Yes, the LTC7060JMSE#PBF supports both logic-level and standard-threshold MOSFETs via its 4V to 14V floating supply range for BST–SW and BGVCC–BGRTN. At 4V, it delivers sufficient gate drive for logic-level devices (VGS(th) ≤ 2.5V); at 10–14V, it fully enhances standard MOSFETs (VGS(th) ≈ 3–4V). The Electrical Characteristics table confirms operational validity across this full range, and the Applications section notes optimization for 10V floating supplies. Drive strength (0.8Ω/1.5Ω) remains effective across the range, though peak current scales linearly with voltage.
What fault conditions trigger the FLT pin on the LTC7060JMSE#PBF, and what is its electrical behavior?
The FLT pin on the LTC7060JMSE#PBF is an open-drain output pulled low (<0.4V) during VCC UVLO/OVLO, BGVCC–BGRTN UVLO, BST–SW UVLO, or thermal shutdown (~180°C). Its typical pull-down resistance is 60Ω, and it releases after a fixed 100 µs delay once all faults clear. An external pull-up resistor (e.g., 51kΩ to VCC) is mandatory. This behavior is documented in the "FAULT FLAG" section and Electrical Characteristics table (RFLTb = 60Ω, tFLTb = 100 µs), ensuring deterministic system-level fault reporting.
LTC7060JMSE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-TSSOP (0.118", 3.00mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- -
- Driven Configuration:
- Half-Bridge
- Channel Type:
- -
- Number of Drivers:
- -
- Gate Type:
- -
- Voltage - Supply:
- 6V ~ 14V
- Logic Voltage - VIL, VIH:
- -
- Current - Peak Output (Source, Sink):
- -
- Input Type:
- -
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- -
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-MSOP-EP
LTC7060JMSE#PBF FAQ
1.How can I place an order for LTC7060JMSE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7060JMSE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7060JMSE#PBF reliable?
The price and inventory of LTC7060JMSE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7060JMSE#PBF is usually 5 days.
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Once your LTC7060JMSE#PBF order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for LTC7060JMSE#PBF?
For technical support, including LTC7060JMSE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7060JMSE#PBF requirements.
6.How does Aetrix verify that LTC7060JMSE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC7060JMSE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7060JMSE#PBF meets industry standards.
7.What is the process for return or replacement of LTC7060JMSE#PBF?
All LTC7060JMSE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7060JMSE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7060JMSE#PBF part is unused and in its original packaging.
Return procedure for LTC7060JMSE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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