STMicroelectronics M74HC373RM13TR
- Part No.:
- M74HC373RM13TR
- Manufacturer:
- STMicroelectronics
- Category:
- Latches
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
M74HC373RM13TR.pdf
- Description:
- IC D-TYPE TRANSP SGL 8:8 20SO
- Quantity:
- Payment:

- Shipping:

Inventory:7,000
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Product details
Overview
M74HC373RM13TR from STMicroelectronics is a high-speed CMOS octal D-type latch with 3-state non-inverting outputs, designed for bus-oriented data latching in digital systems. It operates from 2V to 6V, delivers 12ns typical propagation delay at 6V, supports ±6mA output drive, and features pin- and function-compatibility with standard 74-series 373 devices. Used in microcontroller address/data bus isolation and memory interface control.
For engineers reviewing the M74HC373RM13TR datasheet, M74HC373RM13TR pinout, M74HC373RM13TR application, or M74HC373RM13TR equivalent, key selection criteria include latch enable (LE) and output enable (OE) timing margins, 3-state output leakage (<5µA), VCC=2–6V operating range, and TSSOP20 thermal performance at -55°C to +125°C.
Technical Context
The M74HC373RM13TR implements eight independent D-type latches with dual control: LE determines when input data (D0–D7) is captured and held on Q0–Q7, while OE independently places all outputs in high-impedance state. Its C2MOS silicon gate process enables low ICC (4µA max) and high noise immunity (VNIH/VNIL = 28% VCC min).
Propagation delays tPLH/tPHL are balanced (≤12ns typ. at VCC=6V, CL=50pF), and output transition times (tTLH/tTHL ≤10ns typ. at 6V) support clean signal integrity in synchronous bus architectures. Input setup/hold times (ts=3ns min, th=5ns min at 6V) ensure reliable capture from fast microprocessor buses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Operating Range | 2V to 6V - Enables direct interfacing with 3.3V and 5V logic families without level shifters. |
| tPD Propagation Delay | 12ns (typ.) at VCC=6V, CL=50pF - Supports >30 MHz bus clocking in latch-controlled data paths. |
| IOL/IOH Output Drive | ±6mA (min.) - Sufficient to drive 10 LS-TTL loads or terminate short PCB traces without external buffers. |
| ICC Quiescent Current | 4µA (max.) at TA=25°C - Critical for low-power hold modes in battery-backed or standby systems. |
| VIH/VIL Input Thresholds | 3.15V/1.35V (min/max) at VCC=4.5V - Ensures robust noise margin (>1.3V) in industrial EMI environments. |
| CPD Power Dissipation Cap | 38pF - Predictable dynamic power consumption (ICC(opr) = CPD × VCC × fIN + ICC/8) for thermal budgeting. |
| Operating Temperature | -55°C to +125°C - Qualified for automotive under-hood and industrial motor control applications. |
Pinout & Package
TSSOP20 (Thin Shrink Small Outline Package, 6.5mm × 4.4mm, 0.65mm pitch) with exposed pad for thermal enhancement and mechanical stability in automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE | Active-low 3-state output enable - Asserting high disables all Q outputs into high-Z, enabling bus sharing. |
| 2,5,6,9,12,15,16,19 | Q0–Q7 | Non-inverting latched outputs - Reflect D-input state captured at LE falling edge; tri-stated when OE=H. |
| 3,4,7,8,13,14,17,18 | D0–D7 | Data inputs - Sampled on LE falling edge; must meet ts/th timing relative to LE transition. |
| 11 | LE | Latch enable - Falling edge captures Dn; high level enables transparent mode (Qn follows Dn). |
| 10 | GND | Ground reference - Must be low-impedance return path for all I/O and supply currents. |
| 20 | VCC | Positive supply - Decoupling capacitor (100nF) required within 5mm of pin for AC noise suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical output impedance | |IOH| = IOL = 6mA (min.) - Ensures matched rise/fall times and reduces bus skew in multi-drop configurations. |
| High noise immunity | VNIH = VNIL = 28% VCC (min.) - Tolerates ≥1.2V noise on 4.5V buses, critical for noisy motor-drive or power-supply environments. |
| Balanced propagation delays | tPLH ≅ tPHL - Minimizes duty-cycle distortion in clocked latch chains used for pipeline staging. |
| ESD protection | All inputs protected against static discharge - Meets HBM ≥2kV, eliminating need for external TVS in most board-level layouts. |
| Wide voltage operation | VCC = 2V to 6V - Allows single BOM across 3.3V embedded controllers and legacy 5V industrial backplanes. |
Applications
| Microcontroller Bus Isolation | Memory Address Latching |
|---|---|
Use Scenario: Isolating an 8-bit microcontroller's multiplexed AD bus during instruction fetch cycles. IC Role / Device Role / Timing Role: Acts as transparent latch during LE=H, then holds address bits stable during LE=L while data is read/written. Use Value: Eliminates need for separate address/data demultiplexing logic; supports 12ns timing margin at 6V for 33MHz CPU buses. | Use Scenario: Capturing 8-bit address segments for SRAM or EPROM access in 16-bit memory maps. IC Role / Device Role / Timing Role: Latches lower address byte on LE falling edge; OE controlled by memory select to enable/disable bus drivers. Use Value: Reduces address setup time burden on MCU; 3-state outputs prevent contention during memory refresh or DMA cycles. |
| Industrial I/O Expansion | Legacy Peripheral Interface |
Use Scenario: Buffering parallel GPIO signals from PLC CPU to isolated output modules. IC Role / Device Role / Timing Role: Provides galvanically isolated data staging between controller and field-side drivers via optocoupler-coupled OE/LE. Use Value: Enables deterministic scan-cycle timing with 5ns hold margin; 125°C rating sustains operation near motor drives. | Use Scenario: Interfacing modern microcontrollers to legacy 8-bit peripherals (e.g., LCD controllers, keyboard encoders). IC Role / Device Role / Timing Role: Translates timing-vulnerable control signals into robust, latched strobes compatible with slow peripheral response. Use Value: Compensates for 100ns+ peripheral setup delays using guaranteed 125ns max tPLH at 2V, ensuring first-cycle reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal latch with 3-state output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC373PWR | Same logic function, identical AC/DC specs, but SOIC-20 package (4.4mm × 12.8mm) and higher thermal resistance (θJA = 120°C/W vs. 85°C/W). | Less suitable for space-constrained boards or high-ambient-temperature zones where TSSOP20's lower θJA improves reliability. | Select when board layout allows larger footprint and cost sensitivity outweighs thermal performance. |
| 74LVC373APW | Lower VCC range (1.65–3.6V), faster tPD (5.5ns typ. at 3.3V), but reduced noise margin (VNIH = 20% VCC) and narrower temp range (-40°C to +125°C). | Optimized for 3.3V-only systems; not interoperable with 5V buses due to absolute max VI = VCC+0.5V. | Select only for pure 3.3V designs requiring sub-6ns timing; avoid in mixed-voltage or industrial noise environments. |
Compared with SN74HC373PWR and 74LVC373APW, the M74HC373RM13TR uniquely balances wide voltage operation (2–6V), industrial temperature range (-55°C to +125°C), and TSSOP20 thermal efficiency-making it optimal for legacy-compatible, thermally demanding, or mixed-supply embedded systems.
Availability
M74HC373RM13TR is available at Aetrix Electronics and suitable for microcontroller bus isolation, memory address latching, industrial I/O expansion, and legacy peripheral interface applications requiring stable component supply across extended temperature and voltage ranges.
Supply support for M74HC373RM13TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power discrete solutions with vertical manufacturing capabilities.
The M74HC373RM13TR belongs to ST's high-speed HC logic family, engineered for robustness in harsh environments and backward compatibility with legacy 74-series designs while delivering improved speed and power efficiency.
FAQ
What is the maximum clock frequency supported by M74HC373RM13TR?
The M74HC373RM13TR does not operate on a clock signal-it is edge-triggered by the LE input. Its usable data rate depends on propagation delay (12ns typ. at 6V) and setup/hold timing. With ts=3ns and th=5ns at VCC=6V, it reliably interfaces with microcontrollers running up to 33MHz bus cycles, assuming proper PCB layout and load capacitance ≤50pF.
Can M74HC373RM13TR drive LEDs directly?
No. While its outputs source/sink ±6mA (min.), driving even a single standard LED (typically requiring 10–20mA) exceeds its rated IO and risks violating VOL/VOH specifications. Use external MOSFET or bipolar transistor drivers for LED loads; the device is intended for logic-level bus interfacing, not power switching.
Is M74HC373RM13TR pin-compatible with 74LS373?
Yes-M74HC373RM13TR is functionally and pin-compatible with 74LS373, including identical pinout (TSSOP20 matches DIP-20 pin numbering) and logic behavior. However, voltage levels differ: HC logic requires VIH ≥3.15V at VCC=4.5V, whereas LS logic accepts lower thresholds, so verify input drive strength and noise margins in mixed-technology systems.
Does M74HC373RM13TR require external pull-up resistors on OE or LE?
No. OE and LE are active-low CMOS inputs with negligible leakage (±0.1µA max). They may be driven directly from microcontroller GPIOs or other logic outputs. Pull-ups are unnecessary unless system-level fail-safe behavior (e.g., default high-Z on power-up) is required-then a 10kΩ resistor to VCC suffices.
M74HC373RM13TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74HC
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- D-Type Transparent Latch
- Circuit:
- 8:8
- Output Type:
- Tri-State
- Voltage - Supply:
- 2V ~ 6V
- Independent Circuits:
- 1
- Delay Time - Propagation:
- 12ns
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SO
M74HC373RM13TR FAQ
1.How can I place an order for M74HC373RM13TR through Aetrix?
Please submit a Request for Quotation (RFQ) for M74HC373RM13TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M74HC373RM13TR reliable?
The price and inventory of M74HC373RM13TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M74HC373RM13TR is usually 5 days.
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M74HC373RM13TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M74HC373RM13TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M74HC373RM13TR?
For technical support, including M74HC373RM13TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M74HC373RM13TR requirements.
6.How does Aetrix verify that M74HC373RM13TR is sourced from the original manufacturer or authorized distributors?
All M74HC373RM13TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M74HC373RM13TR meets industry standards.
7.What is the process for return or replacement of M74HC373RM13TR?
All M74HC373RM13TR units undergo pre-shipment inspection (PSI). If there is an issue with M74HC373RM13TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M74HC373RM13TR part is unused and in its original packaging.
Return procedure for M74HC373RM13TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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