STMicroelectronics M74HCT373TTR

Overview

M74HCT373TTR from STMicroelectronics is a high-speed CMOS octal D-type latch with 3-state non-inverting outputs, designed for bus-oriented data latching in digital systems. It features 8-bit transparent latching controlled by LE (latch enable) and OE (output enable), 19 ns typical propagation delay at 4.5 V, ±6 mA output drive, and TTL-compatible input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V). Used in microprocessor address/data bus buffering and memory interface control.

For engineers reviewing the M74HCT373TTR datasheet, M74HCT373TTR pinout, M74HCT373TTR application, or M74HCT373TTR equivalent, key selection criteria include 3-state bus isolation capability, latch timing margins (ts = 4 ns min, th = 5 ns min), output impedance symmetry, operating temperature range (–55°C to +125°C), and TSSOP-20 package compatibility with high-density PCB layouts.

Technical Context

The M74HCT373TTR implements an 8-bit edge-triggered transparent latch architecture where Q outputs follow D inputs while LE is high, and hold the last sampled value when LE transitions low. Its 3-state outputs are independently controlled by active-low OE, enabling bidirectional bus sharing without external logic.

Designed using sub-micron silicon gate C2MOS technology, it achieves symmetrical propagation delays (tPLH ≅ tPHL), balanced output drive (|IOH| = IOL ≥ 6 mA), and low quiescent current (ICC ≤ 4 µA at 25°C), supporting stable operation across –55°C to +125°C with 4.5–5.5 V supply.

Key Specifications

Pinout & Package

TSSOP-20 (Thin Shrink Small Outline Package, 6.5 mm × 4.4 mm, 0.65 mm pitch) with exposed pad not electrically connected; JEDEC MO-153 compliant, RoHS-compliant matte tin lead finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal latch with 3-state output applications.

Compared with SN74HCT373PW and 74VHC373FT, the M74HCT373TTR offers superior timing consistency (19 ns typ. vs. 22 ns max.), guaranteed operation down to –55°C, and tighter VIH/VIL tolerances-making it preferred for mission-critical industrial control and legacy 5 V system upgrades.

Availability

M74HCT373TTR is available at Aetrix Electronics and suitable for microprocessor bus interface, memory address latching, and industrial I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for M74HCT373TTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering intelligent power, analog, MEMS, and microcontroller solutions for automotive, industrial, and consumer markets.

The M74HCT373TTR belongs to ST's HCT logic family, engineered for TTL-compatible 5 V systems requiring low power, high noise immunity, and extended temperature reliability-targeting industrial automation, test equipment, and legacy system modernization.

FAQ

What is the minimum LE pulse width required for reliable latching?

The minimum LE pulse width is 8 ns at VCC = 4.5 V and TA = 25°C, increasing to 22 ns at –55°C to +125°C per AC specifications. This ensures sufficient setup time for internal latch capture; shorter pulses risk metastability or incomplete data transfer to Q outputs.

Can M74HCT373TTR operate with a 3.3 V supply?

No. The M74HCT373TTR is specified only for 4.5–5.5 V operation per Recommended Operating Conditions. At 3.3 V, VIH/VIL thresholds become undefined, output drive drops below specification, and AC performance degrades unpredictably-use 74VHC373 or 74LVC373 for 3.3 V systems.

How does the 3-state output behave during power-up or brownout?

During power-up, outputs remain in high-impedance until VCC reaches ~2.5 V and stabilize; OE and LE states determine final behavior. Under brownout (VCC < 2 V), outputs may enter undefined states-designs must ensure OE is held high or use external pull-downs to avoid bus contention.

Is there a thermal pad on the TSSOP-20 package, and should it be soldered?

No. The M74HCT373TTR TSSOP-20 package (mechanical data c E b A2 A E1 D) has no exposed thermal pad. The package uses standard plastic body construction; thermal dissipation relies on PCB copper area connected to GND/VCC pins-no special pad layout or soldering is required.