STMicroelectronics MASTERGAN1

Overview

MASTERGAN1 from STMicroelectronics is a 600 V system-in-package integrating a half-bridge gate driver and two enhancement-mode GaN HEMTs in a single QFN 9 × 9 × 1 mm package. It delivers R_DS(on) = 150 mΩ (T_J = 25°C), I_D(MAX) = 10 A per transistor, zero reverse recovery charge, and integrated bootstrap diode - enabling high-efficiency, compact resonant LLC and active-clamp flyback converters for server PSUs and telecom rectifiers.

For engineers reviewing the MASTERGAN1 datasheet, MASTERGAN1 pinout, MASTERGAN1 application, or MASTERGAN1 equivalent, key selection criteria include its dual-GaN half-bridge topology, UVLO on both high-side and low-side supplies (V_CC and V_BO), interlocking logic to prevent cross-conduction, thermal shutdown with open-drain SD/OD reporting, and compatibility with 3.3–15 V logic inputs featuring hysteresis and internal pull-downs.

Technical Context

The MASTERGAN1 implements a monolithic half-bridge power stage with independent high-side and low-side GaN drivers, level-shifted via integrated capacitive isolation. Its gate driver features matched propagation delays (<70 ns turn-on/off), programmable deadtime support (>5 ns), and interlocked input logic that forces both outputs low during simultaneous HIN/LIN high states.

Thermal protection uses an on-die sensor with 175°C shutdown threshold and 20°C hysteresis, while UVLO circuits monitor V_CC (4.2–4.75 V turn-on) and V_BO (3.6–4.4 V turn-on) independently - ensuring safe operation under brownout or bootstrap capacitor depletion conditions.

Key Specifications

Pinout & Package

MASTERGAN1 is housed in a thermally enhanced QFN 9 × 9 × 1 mm package with 31 leads and three exposed pads (EP1, EP2, EP3) for GND, SENSE, and VS connections. The package supports high-current routing and efficient heat transfer via soldered thermal vias under EP2 (low-side source) and EP3 (high-side drain).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge GaN power stage applications.

Compared with GS66508T and IMZA65R048M1H, MASTERGAN1 uniquely combines integrated bootstrap diode, hardware interlock, dual UVLO, and open-drain thermal flag in a single QFN - reducing design cycle time by ~3 weeks and eliminating 12+ passives versus discrete alternatives.

Availability

MASTERGAN1 is available at Aetrix Electronics and suitable for server PSUs, telecom rectifiers, and high-power USB-C PD adapters requiring stable component supply, long-term lifecycle assurance, and traceable GaN sourcing.

Supply support for MASTERGAN1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensing solutions for industrial, automotive, and consumer markets.

MASTERGAN1 belongs to ST's MasterGaN family of system-in-package GaN solutions, engineered specifically to accelerate adoption of gallium nitride in high-frequency, high-efficiency power conversion - targeting >98% efficiency and <1 W standby loss in next-generation SMPS.

FAQ

What is the maximum recommended switching frequency for MASTERGAN1?

MASTERGAN1 is characterized for reliable operation up to 2 MHz, with optimal performance observed between 300 kHz and 1 MHz. At 2 MHz, external gate capacitance must remain below 680 pF per side, and minimum input pulse width must exceed 120 ns to ensure clean output transitions without distortion.

Does MASTERGAN1 require external bootstrap diodes?

No - MASTERGAN1 integrates a patented high-voltage DMOS bootstrap diode with 140–175 Ω on-resistance, eliminating the need for external diodes in most applications. An external diode may be added in parallel only for >500 kHz operation where additional current headroom is needed.

How does the SD/OD pin function during thermal shutdown?

During thermal shutdown at 175°C, SD/OD is actively pulled low via an internal open-drain driver. It remains low until junction temperature falls below 155°C (175°C – 20°C hysteresis) and the external controller releases SD/OD above 2.7 V - enabling automatic restart without manual reset.

Can MASTERGAN1 drive asymmetric loads or operate in non-complementary PWM mode?

Yes - MASTERGAN1 supports independent control of HIN and LIN, allowing asymmetric duty cycles, burst-mode operation, and three-state (Hi-Z) output during deadtime. Its interlocking logic only activates when both inputs are high simultaneously, preserving flexibility for advanced modulation schemes.