Analog Devices Inc./Maxim Integrated MAX17000ETG+TG05
- Part No.:
- MAX17000ETG+TG05
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Power Management - Specialized
- Package:
- -
- Datasheet:
-
MAX17000ETG+TG05.pdf
- Description:
- INTEGRATED CIRCUIT
- Quantity:
- Payment:

- Shipping:

Inventory:1,818
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX17000ETG+TG05 from Maxim Integrated is a complete DDR2/DDR3 memory power-management IC integrating a Quick-PWM™ step-down controller (VDDQ), ±2A source/sink LDO (VTT), and ±3mA reference buffer (VTTR) in a single 24-pin TQFN package. It delivers 1.5V or 1.8V VDDQ with 1% accuracy, supports 200–600kHz switching, and enables notebook memory rail sequencing with PGOOD1/PGOOD2 monitoring.
For engineers reviewing the MAX17000ETG+TG05 datasheet, MAX17000ETG+TG05 pinout, MAX17000ETG+TG05 application, or MAX17000ETG+TG05 equivalent, key selection criteria include VDDQ load-transient response (100ns), VTT deadband operation (±5mV), VTTR tracking accuracy (±20mV), thermal shutdown (160°C), and compatibility with DDR/DDR2/DDR3 SSTL-18 and SSTL-15 termination standards.
Technical Context
The MAX17000ETG+TG05 implements a constant-on-time Quick-PWM™ architecture for the VDDQ buck converter, enabling stable operation across wide VIN/VOUT ratios (3V–26V input, 1.0V–2.5V output) while maintaining fixed-frequency behavior and 100ns load-step response. Valley current sensing provides accurate overcurrent protection with 15–25mV threshold tolerance.
Its integrated VTT regulator operates in true source/sink mode with ±5mV deadband and ±2A peak capability, eliminating need for external discharge circuitry during memory standby. VTTR buffers either VCSL/2 or an external 0.5V–1.5V REFIN voltage, supporting flexible DDR bus reference generation with ±20mV accuracy at ±3mA load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDDQ Output Voltage | Preset 1.5V or 1.8V; adjustable 1.0V–2.5V via resistor divider; 1% accuracy over line/load ensures DDR compliance. |
| VDDQ Switching Frequency | 200kHz–600kHz programmable via RTON; enables optimization of efficiency vs. size for notebook PCB layout. |
| VTT Source/Sink Capability | ±2A peak; ±5mV deadband enables fast transient handling for DDR burst loads without excessive output capacitance. |
| VTTR Output Accuracy | ±20mV at ±3mA load; tracks VCSL/2 or REFIN (0.5V–1.5V) to support SSTL-15/18 reference requirements. |
| Fault Protection | Integrated OVP (12–18% trip), UVP (−18% trip), thermal shutdown (160°C), valley current limit (15–25mV), and dual PGOOD comparators. |
| Operating Temperature | −40°C to +85°C; qualified for industrial-grade notebook memory subsystems with full parameter guarantees. |
| Package | 24-pin TQFN-EP, 4mm × 4mm; exposed pad tied to AGND for thermal performance and low-inductance grounding. |
Pinout & Package
MAX17000ETG+TG05 is housed in a 24-pin, 4mm × 4mm TQFN-EP package with exposed thermal pad connected to AGND. Pin functions are validated per Maxim's official datasheet Rev 2 (April 2013).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 OVP | SMPS Overvoltage Control | Enables/disables SMPS OVP and internal discharge FETs; high (>2.4V) activates protection and discharge. |
| 2 PGOOD1 | VDDQ Power-Good Monitor | Open-drain output asserted low if VDDQ deviates >15% from regulation; used for system power sequencing. |
| 3 PGOOD2 | VTT Power-Good Monitor | Open-drain output asserted low if VTT deviates >10% from regulation; enables safe memory initialization. |
| 4 STDBY | Ultra-Skip Mode Control | When high with SHDN high, enables full VDDQ/VTT operation; low forces ultra-skip and disables VTT output. |
| 5 VTTS | VTT Sense Input | Connects to VTT node for accurate regulation to VREFIN or VCSL/2; critical for termination voltage stability. |
| 6 VTTR | Reference Buffer Output | Sources/sinks ±3mA; tracks VCSL/2 or REFIN to provide precise DDR bus reference voltage. |
| 8 VTT | VTT Power Output | ±2A source/sink output; connects directly to memory termination network; requires PGND2 return path. |
| 10 REFIN | External Reference Input | 0.5V–1.5V input sets VTTR/VTTS; tied to VCC for internal VCSL/2 division (SSTL-18 or SSTL-15). |
| 11 FB | VDDQ Feedback Input | Regulates to 1.0V; connect to AGND for 1.5V, VCC for 1.8V, or resistor divider for adjustable output. |
| 14 TON | Frequency Setting Input | Resistor-to-VIN sets switching frequency (200–600kHz); enables trade-off between efficiency and EMI. |
| 15 DH / 18 DL | Gate Drivers | DH drives high-side MOSFET (BST–LX swing); DL drives synchronous rectifier (VDD–PGND1 swing). |
| 19 VDD | DL Gate Driver Supply | +4.5V to +5.5V supply for low-side driver; bypassed with ≥1μF ceramic capacitor to PGND1. |
| 23 VCC | Main Controller Supply | +4.5V to +5.5V analog supply; bypassed to AGND; UVLO triggers at 4.0V–4.4V. |
| 24 SHDN | Global Shutdown Control | Pulled high for normal operation; falling edge initiates soft-stop ramp and enters <1μA shutdown state. |
Key Features
| Feature | Design Value |
|---|---|
| Quick-PWM™ Architecture | 100ns load-step response with fixed-frequency behavior avoids instability in low-duty-cycle DDR applications. |
| VTT ±5mV Deadband | Eliminates unnecessary switching during small load changes, reducing noise and output capacitance by up to 50%. |
| Dual Independent PGOOD Outputs | PGOOD1 (VDDQ) and PGOOD2 (VTT) enable sequential power-up and fault-isolation in DDR memory systems. |
| Three Operating Modes | SKIP (efficiency), forced-PWM (low noise), and ultra-skip/standby (≤4mA quiescent) support dynamic power states. |
| Integrated Discharge FETs | Internal MOSFETs discharge VDDQ and VTT on shutdown when OVP = high, meeting JEDEC DDR timing requirements. |
Applications
| DDR2 Notebook Memory Supply | DDR3 SSTL-15 Termination System |
|---|---|
|
Use Scenario: Powering DDR2 SDRAM modules in ultraportable notebooks with 7V–20V input rails. IC Role / Device Role / Timing Role: Generates VDDQ (1.8V), VTT (0.9V), and VTTR (0.9V) with synchronized startup and independent fault monitoring. Use Value: Eliminates discrete regulators and sequencing ICs; reduces BOM count by 3–5 components while meeting JEDEC tVR/tVF specs. |
Use Scenario: Providing termination voltage for DDR3 memory subsystems operating at 1.5V I/O with tight VTT regulation. IC Role / Device Role / Timing Role: Delivers ±2A VTT with ±5mV deadband and 160μs soft-start to meet DDR3 tINIT and tZQCAL timing windows. Use Value: Enables single-chip VTT sourcing/sinking without external op-amps or discharge resistors, cutting board area by 35%. |
| SSTL-18 Reference Generation | Notebook Standby Power Management |
|
Use Scenario: Generating stable 0.9V reference for DDR2 memory controllers using SSTL-18 signaling standard. IC Role / Device Role / Timing Role: VTTR buffer sources ±3mA at ±20mV accuracy while tracking VCSL/2, decoupled with 0.33μF ceramic cap. Use Value: Replaces discrete op-amp + reference IC solutions; achieves 0.01% drift over −40°C to +85°C without calibration. |
Use Scenario: Maintaining memory retention during S3 suspend-to-RAM in Windows-based notebooks. IC Role / Device Role / Timing Role: Enters ultra-skip mode (≤4mA ICC) with VTT disabled and VDDQ in low-quiescent regulation. Use Value: Reduces memory subsystem standby power by 65% vs. conventional buck+LDO solutions, extending battery life. |
Availability
MAX17000ETG+TG05 is available at Aetrix Electronics and suitable for DDR2/DDR3 memory power supplies, notebook computer motherboard designs, and SSTL-15/18 termination systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MAX17000ETG+TG05 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power-management ICs for computing, communications, and industrial applications.
The MAX17000 product line was designed specifically for DDR/DDR2/DDR3 memory power delivery in space-constrained notebook platforms, integrating three critical rails into one monolithic solution with JEDEC-compliant sequencing and protection.
FAQ
What is the maximum input voltage rating for the MAX17000ETG+TG05?
The MAX17000ETG+TG05 supports an absolute maximum input voltage of 26V on the VIN pin, with recommended operating range of 3V to 26V. This allows direct connection to common notebook adapter rails (7V–20V) while providing margin for transients. The VCC and VDD supplies are limited to 4.5V–5.5V and must be independently regulated.
How does the MAX17000ETG+TG05 achieve 100ns load-step response on VDDQ?
The MAX17000ETG+TG05 achieves 100ns VDDQ load-step response through its proprietary Quick-PWM™ constant-on-time architecture, which eliminates loop compensation delays inherent in voltage-mode or current-mode PWMs. The controller senses inductor current directly and adjusts duty cycle within one switching cycle, enabling rapid correction without sacrificing frequency stability.
Can the MAX17000ETG+TG05 support both DDR2 and DDR3 memory simultaneously?
No - the MAX17000ETG+TG05 is configured per application: VDDQ output is set to either 1.5V (DDR2/SSTL-15) or 1.8V (DDR2/SSTL-18) via FB pin connection, and VTTR/VTTS track accordingly. A single MAX17000ETG+TG05 cannot dynamically switch between DDR2 and DDR3 standards; design selection is fixed at layout.
What is the purpose of the VTTS pin on the MAX17000ETG+TG05?
The VTTS pin on the MAX17000ETG+TG05 is the VTT output sense terminal. It must be connected directly to the VTT net near the memory DIMM to close the feedback loop for accurate regulation. This Kelvin sensing eliminates IR drop errors from PCB traces, ensuring ±5mV deadband operation and stable termination under dynamic load conditions.
Does the MAX17000ETG+TG05 include thermal protection?
Yes, the MAX17000ETG+TG05 includes thermal shutdown protection with a trip threshold of 160°C and 15°C hysteresis. When junction temperature exceeds 160°C, the device disables all outputs and enters a latched fault state until SHDN is cycled. This protects against sustained overload or inadequate heatsinking in compact notebook layouts.
MAX17000ETG+TG05 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Applications:
- -
- Current - Supply:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
MAX17000ETG+TG05 FAQ
1.How can I place an order for MAX17000ETG+TG05 through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX17000ETG+TG05 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX17000ETG+TG05 reliable?
The price and inventory of MAX17000ETG+TG05 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX17000ETG+TG05 is usually 5 days.
3.What payment methods are accepted for MAX17000ETG+TG05?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX17000ETG+TG05 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX17000ETG+TG05?
MAX17000ETG+TG05 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX17000ETG+TG05 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX17000ETG+TG05?
For technical support, including MAX17000ETG+TG05 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX17000ETG+TG05 requirements.
6.How does Aetrix verify that MAX17000ETG+TG05 is sourced from the original manufacturer or authorized distributors?
All MAX17000ETG+TG05 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX17000ETG+TG05 meets industry standards.
7.What is the process for return or replacement of MAX17000ETG+TG05?
All MAX17000ETG+TG05 units undergo pre-shipment inspection (PSI). If there is an issue with MAX17000ETG+TG05, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX17000ETG+TG05 part is unused and in its original packaging.
Return procedure for MAX17000ETG+TG05:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX17000ETG+TG05 Tags

-
TPS2511DGNR
Texas Instruments

-
UTC2000/MG
Microchip Technology

-
TUSB320HAIRWBR
Texas Instruments

-
TPS61252DSGR
Texas Instruments

-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments

-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments

-
STUSB1600AQTR
STMicroelectronics

-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments

-
TPS65150PWPR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

