Analog Devices Inc./Maxim Integrated MAX5940AESA+
- Part No.:
- MAX5940AESA+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Power Over Ethernet (PoE) Controllers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
MAX5940AESA+.pdf
- Description:
- IC POE CNTRL 1 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,563
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Product details
Overview
MAX5940AESA+ from Maxim Integrated is an IEEE 802.3af-compliant powered device (PD) interface controller for Power-over-Ethernet systems. It provides detection signature, classification signature, and integrated isolation switch with programmable inrush current control. Features fixed UVLO threshold (35.4V turn-on), 80V absolute maximum rating, <10µA detection leakage, and operates over –40°C to +85°C - used in IP phones and security cameras.
For engineers reviewing the MAX5940AESA+ datasheet, MAX5940AESA+ pinout, MAX5940AESA+ application, or MAX5940AESA+ equivalent, this page delivers verified technical context, real-world timing behavior under twisted-pair voltage drop, confirmed MOSFET on-resistance (1.5Ω max at +85°C), PGOOD open-drain logic referencing OUT, and exact classification current thresholds per RCLASS resistor value.
Technical Context
The MAX5940AESA+ implements three sequential operational modes: detection (1.4–10.1V input), classification (12.6–20V), and power mode (VIN > 35.4V). Detection uses a 25.5kΩ signature resistor with <10µA offset current; classification sets PD class via RCLASS-to-VEE resistor (0–4), delivering precise current ranges (e.g., Class 3: 26.45–29.55mA).
In power mode, it drives an internal N-channel MOSFET with 10µA gate-charge current, limiting inrush via external CGATE capacitor. Its fixed UVLO (35.4V ON / 30V OFF) includes 5.4V hysteresis and 0.32ms deglitch time to reject noise from cable resistance drop during mode transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Detection Offset Current | <10µA - ensures reliable PSE slope measurement (ΔV/ΔI) without false-negative detection |
| Classification Current Range | Class 3: 26.45–29.55mA - enables accurate IEEE 802.3af Class 3 power allocation (6.49–12.95W) |
| UVLO Turn-On Threshold | 35.4V (fixed) - guarantees stable power-mode entry after PSE applies valid PoE voltage |
| MOSFET On-Resistance | 1.5Ω max at +85°C - limits conduction loss and thermal rise under 300mA load current |
| PGOOD Reference | Referenced to OUT - allows direct interfacing with DC-DC converter ON pins without level-shifting |
| Absolute Max Rating | 80V on GND pin - supports robust operation across worst-case PoE transients and cable drop |
| Operating Temp Range | –40°C to +85°C - qualified for industrial and outdoor IP camera deployments |
Pinout & Package
MAX5940AESA+ is housed in an 8-pin SOIC (SO) package, 0.150" wide, with exposed pad not present. Pin 1 is UVLO; Pin 2 is RCLASS; Pin 3 is GATE; Pin 4 is VEE; Pin 5 is OUT; Pin 6 is PGOOD; Pins 1 and 7 are No Connect (N.C.) for MAX5940A/MAX5940C variants; Pin 8 is GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | UVLO | Fixed-threshold undervoltage lockout input - tied to VEE for default 35.4V turn-on; no external programming |
| 2 | RCLASS | Classification current setting node - connects to VEE via precision resistor (e.g., 255Ω for Class 3) |
| 3 | GATE | Internal N-MOSFET gate drive - sources 10µA to charge external CGATE for inrush control |
| 4 | VEE | Negative supply rail - connects to -48V PoE return; source terminal of internal isolation MOSFET |
| 5 | OUT | Power output - drain of internal MOSFET; delivers regulated PoE power to downstream circuitry |
| 6 | PGOOD | Active-high open-drain power-good signal - asserted when VOUT within 1.2V of VEE and VGATE > 5V above VEE |
| 7 | N.C. | No internal connection - must remain unconnected; not used in MAX5940A/MAX5940C |
| 8 | GND | Positive input terminal - connects to PoE +48V return path; forms VIN = GND − VEE differential input |
Key Features
| Feature | Design Value |
|---|---|
| Fully integrated 802.3af PD interface | Eliminates need for discrete detection/classification resistors, external MOSFET, and UVLO comparators |
| Programmable classification signature | Supports all five IEEE classes via single RCLASS resistor - enables flexible power budgeting per application |
| Integrated isolation MOSFET | On-resistance ≤1.5Ω at +85°C - reduces conduction loss and simplifies BOM vs. discrete FET solutions |
| Wide UVLO hysteresis (5.4V) | Compensates for up to ~5V IR drop across 100m twisted-pair cable - prevents false power-down during load transients |
| PGOOD referenced to OUT | Enables direct enable control of downstream DC-DC converters without level-shifters or pull-up to GND |
Applications
| IP Phones | Security Cameras |
|---|---|
Use Scenario: Powered via PoE switch in enterprise VoIP deployment with centralized UPS backup. IC Role / Device Role / Timing Role: PD interface controller managing detection, classification, and clean power ramp-up before codec/processor initialization. Use Value: Ensures compliant 15.4W power draw (Class 3), eliminates external surge protection components, and maintains PSE link integrity during call setup. |
Use Scenario: Outdoor PTZ camera powered over 80m Cat5e cable with voltage drop up to 4.8V. IC Role / Device Role / Timing Role: Provides glitch-free transition from detection → classification → power-on using 0.32ms UVLO deglitch and wide hysteresis. Use Value: Prevents camera reset during transient dips; <10µA detection leakage avoids PSE misclassification. |
| Wireless Access Nodes | Computer Telephony |
Use Scenario: Dual-band 802.11ac AP mounted on ceiling with PoE+ injector and local thermal stress. IC Role / Device Role / Timing Role: Controls inrush current via GATE/CGATE to limit peak input surge during hot-plug events. Use Value: Reduces stress on upstream PoE PSE port; 1.5Ω MOSFET RDS(on) minimizes self-heating at full 300mA load. |
Use Scenario: USB phone adapter drawing PoE power while maintaining USB audio latency requirements. IC Role / Device Role / Timing Role: Generates PGOOD referenced to OUT to enable low-noise LDO only after stable rail is established. Use Value: Avoids brown-out resets during PHY initialization; fixed UVLO ensures deterministic power-on sequence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PD interface controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX5940CESA+ | Same pinout, same fixed UVLO (35.4V), but 90V absolute max rating vs. 80V | Required for designs needing higher transient immunity (e.g., industrial PoE with >80V surges) | Select MAX5940CESA+ only if system-level surge testing exceeds 80V; otherwise MAX5940AESA+ suffices. |
| LT4275IMS#PBF | Adjustable UVLO, dual PGOOD/PGOOD outputs, 100V abs max, different pinout and classification method | Supports IEEE 802.3at (PoE+) with higher current classes and dynamic power negotiation | Choose LT4275IMS#PBF for PoE+ upgrades; MAX5940AESA+ remains optimal for cost-sensitive 802.3af-only designs. |
Compared with MAX5940CESA+, MAX5940AESA+ trades 10V lower absolute rating for tighter cost control and identical functional behavior in standard 802.3af deployments; versus LT4275IMS#PBF, it offers simpler configuration and lower BOM count but lacks PoE+ support and requires redesign for pin compatibility.
Availability
MAX5940AESA+ is available at Aetrix Electronics and suitable for IP phones, security cameras, wireless access nodes, and computer telephony requiring stable component supply across extended temperature and PoE transient conditions.
Supply support for MAX5940AESA+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs high-performance analog and mixed-signal ICs for power, interface, and sensing applications, with focus on reliability and integration density.
The MAX5940 family targets IEEE 802.3af Power-over-Ethernet powered devices, delivering fully integrated detection, classification, and power-switching functionality in minimal footprint for space-constrained endpoints.
FAQ
What is the UVLO threshold of the MAX5940AESA+?
The MAX5940AESA+ features a fixed undervoltage lockout threshold of 35.4V (typical turn-on) with 5.4V hysteresis, resulting in a 30V turn-off point. This threshold is factory-set and cannot be adjusted externally - unlike MAX5940B/MAX5940D variants which support resistor-divider programming. The MAX5940AESA+ uses this fixed threshold to ensure consistent power-mode entry across all operating temperatures from –40°C to +85°C.
Does the MAX5940AESA+ support IEEE 802.3at (PoE+)?
No, the MAX5940AESA+ is designed exclusively for IEEE 802.3af compliance and does not support 802.3at (PoE+) features such as higher power classes (up to 30W), autoclass, or dynamic power negotiation. Its classification current range tops out at Class 4 (36.6–41.4mA), which remains reserved per 802.3af and is not implemented for active use. For PoE+ applications, designers should consider alternatives like the LT4275 or MAX5980 series.
How is the classification current set on the MAX5940AESA+?
The MAX5940AESA+ sets classification current by connecting a precision resistor (RCL) between the RCLASS pin and VEE. For example, a 255Ω ±1% resistor configures Class 3, delivering 26.45–29.55mA at VIN = 12.6–20V. The MAX5940AESA+ datasheet Table 2 specifies exact RCL values and corresponding current ranges for Classes 0–4. No additional components or configuration registers are required - the resistor alone determines the PD's power class.
What is the purpose of the GATE pin on the MAX5940AESA+?
The GATE pin on the MAX5940AESA+ drives the internal N-channel MOSFET's gate with a 10µA constant-current source. Connecting an external capacitor (CGATE) between GATE and OUT controls the MOSFET's turn-on slew rate, thereby limiting inrush current into downstream capacitance. This eliminates the need for external inrush-limiting circuits. Pulling GATE to VEE disables the MOSFET while preserving detection and classification functionality - useful for system-level power sequencing.
Can the MAX5940AESA+ operate without an external diode bridge?
Yes, the MAX5940AESA+ is explicitly designed to operate with or without an external diode bridge, as stated in its datasheet. Its internal architecture accommodates both configurations: polarity-insensitive detection and classification signatures, plus proper handling of reversed input voltage via optional external protection diodes. This flexibility simplifies design for applications where bridge rectifiers add cost or board space - such as compact IP phones or low-power sensors.
MAX5940AESA+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Controller (PD)
- Number of Channels:
- 1
- Power - Max:
- 12.95 W
- Internal Switch(s):
- Yes
- Auxiliary Sense:
- No
- Standards:
- 802.3af (PoE)
- Voltage - Supply:
- 36.6V ~ 67V
- Current - Supply:
- 400µA
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
MAX5940AESA+ FAQ
1.How can I place an order for MAX5940AESA+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX5940AESA+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX5940AESA+ reliable?
The price and inventory of MAX5940AESA+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX5940AESA+ is usually 5 days.
3.What payment methods are accepted for MAX5940AESA+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX5940AESA+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX5940AESA+?
MAX5940AESA+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX5940AESA+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX5940AESA+?
For technical support, including MAX5940AESA+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX5940AESA+ requirements.
6.How does Aetrix verify that MAX5940AESA+ is sourced from the original manufacturer or authorized distributors?
All MAX5940AESA+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX5940AESA+ meets industry standards.
7.What is the process for return or replacement of MAX5940AESA+?
All MAX5940AESA+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX5940AESA+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX5940AESA+ part is unused and in its original packaging.
Return procedure for MAX5940AESA+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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