My Inquiry
My Account
Analog Devices Inc./Maxim Integrated MAX5992AETG+T
- Part No.:
- MAX5992AETG+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Power Over Ethernet (PoE) Controllers
- Package:
- -
- Datasheet:
-
MAX5992AETG+T.pdf
- Description:
- IC MULTISOURCE CONTROLLER QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,807
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX5992AETG+T from Maxim Integrated is a IEEE 802.3af/at-compliant powered device (PD) controller for Power-over-Ethernet systems, featuring 38.6V PoE UVLO threshold, integrated active FET bridge control, 2-level current limit (800mA/1.9A), and intelligent maintain power signature (MPS) supporting ≤14mA pulse current at 75% duty cycle. It enables high-power IP security cameras and wireless access nodes with seamless wall adapter switchover.
For engineers reviewing the MAX5992AETG+T datasheet, MAX5992AETG+T pinout, MAX5992AETG+T application, or MAX5992AETG+T equivalent, key selection considerations include PoE classification support (Class 0–5), dual inrush-current modes for FTTH/FTTB redundancy, ultra-low-power sleep mode with 6.5s delay, and 24-pin TQFN package thermal performance (θJA = 36°C/W).
Technical Context
The MAX5992AETG+T implements a full IEEE 802.3af/at PD interface with detection (24.9kΩ signature), 2-event classification (mark/reset thresholds at 10.8V/4V), and power-on sequencing including 90–110ms PG delay and 8ms current-limit timeout. Its active FET bridge control uses VIN1/VIN2 differential sensing (100mV threshold) to drive four external MOSFET gates (NDR1/NDR2/PDR1/PDR2) with 8–11V gate drive voltage.
It integrates dual UVLO configurations: 38.6V nominal PoE turn-on (MAX5992A variant) and selectable 20.8V industrial threshold via ADJ_UVLO pin; input overvoltage protection triggers at 65V with 4.5V hysteresis and 170µs deglitch. Sleep/ultra-low-power sleep modes are controlled by SL/ULP pins, enabling LED pulsing (250Hz, 25% duty) and MPS current (10–14mA) while maintaining <2.5mA quiescent supply current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PoE UVLO Threshold | 38.6V (MAX5992A variant); enables reliable startup under twisted-pair cable drop without false triggering |
| Classification Support | IEEE 802.3af/at Class 0–5; uses external RCLS resistor to set precise current levels per class table |
| Current Limit Options | 800mA (CL_SEL open) or 1.9A (CL_SEL to VSS); foldback starts at 11V output to protect downstream DC-DC |
| MPS Current | 10–14mA at 75% duty cycle; sustains PSE recognition during sleep/ultra-low-power sleep without auxiliary power |
| Package & Thermal | 24-pin TQFN (4mm × 4mm); θJA = 36°C/W on 4-layer board; supports 2222mW dissipation at +70°C |
| Operating Temperature | -40°C to +85°C; junction limit +150°C with 20°C thermal shutdown hysteresis |
| Input Voltage Range | 60V max continuous; withstands 100V transient; RJ45 12V mode enabled only on MAX5992B |
Pinout & Package
MAX5992AETG+T is housed in a 24-pin, 4mm × 4mm TQFN package with exposed pad (EP) connected to VSS for thermal management. The package supports surface-mount assembly and meets RoHS requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD / VSS | Positive/negative supply inputs | Connect to active FET bridge outputs; require ≥68nF bypass capacitor on VDD–VSS |
| DET / CLS | Detection and classification resistor inputs | DET accepts 24.9kΩ signature resistor; CLS sets classification current via RCLS (e.g., 615Ω for Class 0) |
| SENSE / GATE | Current-sense input and isolation MOSFET gate driver | SENSE connects to MOSFET source and 100mΩ sense resistor; GATE drives external N-channel MOSFET gate |
| VIN1 / VIN2 | Active FET bridge voltage-sensing inputs | Differential polarity detection (threshold 100mV) selects nFET/pFET pair; enables back-powering protection |
| NDR1/NDR2/PDR1/PDR2 | Active bridge gate-control outputs | Drive four external MOSFETs; NDRx for nFETs, PDRx for pFETs; each provides 8–11V gate drive |
| SL / ULP | Sleep and ultra-low-power enable inputs | SL falling edge (MAX5992A) or 6.5s low (MAX5992B) initiates sleep; ULP acts as wake trigger |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 802.3af/at & UPoE compliance | Fully implements detection, 2-event classification, and power-on sequencing per standard; supports Universal PoE higher-power delivery |
| Integrated active FET bridge control | Drives four external MOSFETs with polarity-aware logic; prevents back-powering and enables redundant multi-PD operation |
| Selectably configurable UVLO | 38.6V PoE UVLO (MAX5992A) or 20.8V industrial UVLO via ADJ_UVLO pin; wide hysteresis (3.2V) rejects cable-drop noise |
| Intelligent maintain power signature (MPS) | Generates 10–14mA, 75% duty cycle current pulses during sleep/ultra-low-power modes; eliminates need for auxiliary bias |
| Seamless wall adapter transition | WAD input detects >8V wall adapter; WAD_SEL pin configures priority (PoE-first or wall-first); 2EC output signals source presence |
| Ultra-low-power sleep mode | Reduces supply current below 2.5mA while sustaining MPS and LED pulsing (250Hz, 25% duty, programmable 10–20mA) |
Applications
| IP Security Cameras (IPC) | Wireless Access Nodes |
|---|---|
Use Scenario: Outdoor PoE-powered camera with motion-triggered recording and night vision requiring sustained low-power standby. IC Role / Device Role / Timing Role: PD controller managing IEEE 802.3at classification, active bridge rectification, and MPS maintenance during deep sleep. Use Value: Enables 14mA MPS current at 75% duty cycle to retain PSE link without auxiliary power, reducing BOM cost and board space. |
Use Scenario: Dual-band Wi-Fi 6 access point deployed in ceiling-mounted PoE infrastructure with thermal constraints. IC Role / Device Role / Timing Role: High-efficiency PD interface providing 2-event classification, 1.9A inrush current limit, and thermal shutdown at +150°C. Use Value: Active FET bridge control minimizes conduction loss; 36°C/W θJA allows operation in confined enclosures without forced cooling. |
| Fiber-to-the-Home (FTTH) | High-Power 2x2P PD Systems |
Use Scenario: Residential gateway with redundant PoE inputs (primary + backup) requiring glitch-free failover. IC Role / Device Role / Timing Role: Redundancy manager using RDCY_SEL to configure dual inrush timing and SIG_OK synchronization across multiple PDs. Use Value: Selectable inrush modes prevent simultaneous surge currents; SIG_OK pin enables inter-device coordination for synchronized startup. |
Use Scenario: Enterprise-grade video conferencing endpoint drawing >25W via two PoE ports (2x2P) with strict thermal limits. IC Role / Device Role / Timing Role: Dual-port PD controller coordinating power delivery using SIG_OK handshake and active bridge polarity detection. Use Value: VIN1/VIN2 differential sensing (100mV threshold) ensures correct FET pairing regardless of cable polarity; supports UPoE power aggregation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar powered device controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX5992BETG+T | 35.4V PoE UVLO; includes RJ45 12V mode (8.7V threshold) and fixed 6.5s sleep delay; same pinout and package | Better suited for industrial 12V PoE deployments and applications requiring guaranteed sleep timing | Select MAX5992BETG+T when 12V PoE compatibility or deterministic 6.5s sleep entry is required |
| LT4275AIMSE#TRPBF | IEEE 802.3bt-compliant; supports up to Class 8 (90W); no integrated active bridge control; requires external MOSFET drivers | Targets next-gen high-power UPoE devices where >25.5W delivery and 4-pair power are mandatory | Choose LT4275AIMSE#TRPBF for future-proofing beyond 802.3at and when external bridge design flexibility is preferred |
Compared with MAX5992BETG+T, the MAX5992AETG+T offers higher 38.6V UVLO for improved noise immunity in long-cable installations, while LT4275AIMSE#TRPBF extends power capability to 90W but increases system complexity with external FET control.
Availability
MAX5992AETG+T is available at Aetrix Electronics and suitable for IP security cameras, wireless access nodes, and fiber-to-the-home gateways requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for industrial and telecom deployments.
Supply support for MAX5992AETG+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding industrial, communications, and computing applications.
The MAX5992A/MAX5992B product line delivers high-performance, multisource PD controllers optimized for IEEE 802.3af/at and UPoE systems requiring robust cable-drop compensation, redundancy support, and ultra-low-power sleep operation.
FAQ
What is the PoE UVLO threshold for MAX5992AETG+T?
The MAX5992AETG+T has a nominal PoE undervoltage lockout (UVLO) threshold of 38.6V, with ±1.6V tolerance. This value is fixed for the MAX5992A variant and differs from the MAX5992B's 35.4V threshold. The UVLO hysteresis is 3.2V, ensuring stable turn-on/turn-off behavior despite twisted-pair resistive drop. The MAX5992AETG+T also supports an industrial 20.8V UVLO mode when ADJ_UVLO is pulled to VSS.
How does MAX5992AETG+T support 2-event classification for IEEE 802.3at compliance?
The MAX5992AETG+T implements full 2-event classification by responding to Type 2 PSE probing with two distinct current signatures: first, the programmed classification current (e.g., 52.7–63.3mA for Class 5), then a mark current (1.0–3.5mA) when input voltage falls below 10.8V. The reset event occurs below 4V. This sequence is automatically generated without external timing components, and the 2EC pin asserts a 1.5mA sink during both events to signal PSE detection.
Can MAX5992AETG+T drive external MOSFETs for active bridge rectification?
Yes, the MAX5992AETG+T integrates complete active FET bridge control logic and four dedicated gate drivers: NDR1/NDR2 for n-channel MOSFETs and PDR1/PDR2 for p-channel MOSFETs. It senses polarity across VIN1/VIN2 (100mV threshold) to activate the correct FET pair, enabling efficient rectification, back-powering protection, and support for redundant multi-PD architectures without external controllers.
What is the function of the SIG_OK pin on MAX5992AETG+T?
The SIG_OK pin on MAX5992AETG+T serves as both input and output for synchronization in high-power 2x2P PD systems. When VIN exceeds the UVLO threshold, SIG_OK is internally pulled high to indicate valid power. In multi-PD configurations, it connects directly to another MAX5992AETG+T's SIG_OK pin to coordinate inrush timing and prevent simultaneous current surges. It must be left unconnected in single-PD applications.
Does MAX5992AETG+T support seamless power transition between PoE and wall adapter?
Yes, the MAX5992AETG+T supports seamless switchover via its WAD (wall adapter detect) input and WAD_SEL pin. When a >8V wall adapter is detected at WAD, the isolation MOSFET turns off and 2EC sinks current. With WAD_SEL unconnected, PoE is primary; with WAD_SEL tied to VSS, wall adapter takes priority only when its voltage exceeds PoE voltage-enabling flexible power-source arbitration without firmware intervention.
MAX5992AETG+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- -
- Number of Channels:
- -
- Power - Max:
- -
- Internal Switch(s):
- -
- Auxiliary Sense:
- -
- Standards:
- -
- Voltage - Supply:
- -
- Current - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
MAX5992AETG+T FAQ
1.How can I place an order for MAX5992AETG+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX5992AETG+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX5992AETG+T reliable?
The price and inventory of MAX5992AETG+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX5992AETG+T is usually 5 days.
3.What payment methods are accepted for MAX5992AETG+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX5992AETG+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX5992AETG+T?
MAX5992AETG+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX5992AETG+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX5992AETG+T?
For technical support, including MAX5992AETG+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX5992AETG+T requirements.
6.How does Aetrix verify that MAX5992AETG+T is sourced from the original manufacturer or authorized distributors?
All MAX5992AETG+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX5992AETG+T meets industry standards.
7.What is the process for return or replacement of MAX5992AETG+T?
All MAX5992AETG+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX5992AETG+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX5992AETG+T part is unused and in its original packaging.
Return procedure for MAX5992AETG+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX5992AETG+T Tags
-
TPS2378DDAR
Texas Instruments
-
TPS23753APWR
Texas Instruments
-
TPS23756PWPR
Texas Instruments
-
TPS23750PWPR
Texas Instruments
-
MP8007GV-Z
Monolithic Power Systems Inc.
-
TPS23861PWR
Texas Instruments
-
TPS23753PWR
Texas Instruments
-
PD69201ILD-TR
Microchip Technology
-
SI3402-B-GM
Skyworks Solutions Inc.
-
SI3402-B-GMR
Skyworks Solutions Inc.
-
SI34071-A01-GMR
Skyworks Solutions Inc.
-
SI3404-A-GMR
Skyworks Solutions Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
