My Inquiry
My Account
Analog Devices Inc./Maxim Integrated MAX8660ETL+C7J
- Part No.:
- MAX8660ETL+C7J
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Power Management - Specialized
- Package:
- -
- Datasheet:
-
MAX8660ETL+C7J.pdf
- Description:
- INTEGRATED CIRCUIT
- Quantity:
- Payment:
- Shipping:
Inventory:4,836
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX8660ETL+C7J from Maxim Integrated is a high-efficiency, low-quiescent-current power management IC (PMIC) designed to power application processors in smart cellular phones and portable devices. It integrates four synchronous step-down DC-DC converters (REG1–REG4), four LDO regulators (REG5–REG8), and an always-on 3.3V/30mA LDO (V8), with dynamic voltage management via I²C for processor core (V3) and SRAM (V4) rails. Key confirmed parameters: 2MHz PWM switching, 20µA deep-sleep current, 7.5V input protection, -40°C to +85°C operation, and 40-pin Thin QFN (5mm × 5mm).
For engineers reviewing the MAX8660ETL+C7J datasheet, MAX8660ETL+C7J pinout, MAX8660ETL+C7J application, or MAX8660ETL+C7J equivalent, this page delivers verified technical context on its Marvell PXA3xx-optimized power sequencing, I²C-programmable output voltages (e.g., V3: 0.725–1.8V, V4: 0.725–1.8V), forced-PWM noise control, and integrated low-battery detection (LBO/LBF) - all critical for mobile SoC power architecture validation.
Technical Context
The MAX8660ETL+C7J implements four independent synchronous buck converters using p-channel/n-channel MOSFETs with programmable soft-start ramp rates (e.g., 8 mV/µs for V3/V4), 16.7–100% duty-cycle range, and automatic PWM-to-skip mode transition at light load. Each converter supports dynamic voltage scaling via I²C register writes (e.g., DVM Voltage Change Register at 0x20) and features dedicated enable logic (EN1–EN5, EN34) and power-good monitoring (PG1–PG4).
Its linear regulator subsystem includes REG5 (1.8V/200mA LDO for MVT/OSC/PLL), dual programmable card LDOs (REG6/REG7: 1.8–3.3V/500mA each), and REG8 - a dedicated always-on 3.3V/30mA LDO powered directly from main battery (IN8). All LDOs incorporate internal off-discharge resistors (e.g., 2kΩ for REG5, 350Ω for REG6/REG7) and support I²C-controlled voltage selection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.6V to 6.0V - supports single-cell Li-ion (3.0–4.2V) and extended input up to 6V without external clamping |
| PWM Switching Frequency | 2.0MHz ±5% - enables use of compact 1µH inductors and 4.7µF ceramic output capacitors |
| Deep-Sleep Quiescent Current | 20µA - sustains V8 rail only, minimizing battery drain during system suspend |
| V3 Output Range (I²C) | 0.725V to 1.8V - dynamically adjusts processor core voltage per workload, reducing active power by >30% vs fixed rail |
| V4 Output Range (I²C) | 0.725V to 1.8V - independently scales SRAM supply to match memory access patterns |
| Overvoltage Lockout | 6.35V threshold - shuts down all regulators before damage occurs at 7.5V absolute max input |
| Low-Battery Detection | 1.200V falling threshold (±18mV) - triggers LBO assertion to initiate graceful shutdown before brownout |
Pinout & Package
MAX8660ETL+C7J is housed in a 40-pin Thin QFN package (5mm × 5mm × 0.8mm) with exposed thermal pad (EP). Pin functions are validated per Maxim's official pin configuration diagram and functional description.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | REG1 output (I/O/memory rail) | Pin-programmable 3.3V/3.0V/2.85V @ 1.2A; SET1 selects voltage via logic level |
| V2 | REG2 output (I/O/memory rail) | Pin-programmable 3.3V/2.5V/1.8V @ 0.9A; SET2 selects voltage via logic level |
| V3 | REG3 output (processor core) | I²C-programmable 0.725–1.8V @ 1.6A; supports dynamic voltage management (DVM) |
| V4 | REG4 output (SRAM) | I²C-programmable 0.725–1.8V @ 0.4A; independent DVM control for memory subsystem |
| V5 | REG5 output (MVT/OSC/PLL) | I²C-programmable 1.7–2.0V @ 200mA; low-noise LDO with 40dB PSRR at 10kHz |
| V6/V7 | REG6/REG7 outputs (card interfaces) | I²C-programmable 1.8–3.3V @ 500mA each; supports SDIO, MMC, or USB PHY supplies |
| V8 | REG8 output (always-on battery rail) | Fixed 3.3V @ 30mA; powered directly from IN8 to maintain RTC/backup registers during main power loss |
| SCL/SDA | I²C serial interface | Standard 2-wire bus (up to 400kHz) for real-time voltage reprogramming and status readback |
| LBO/LBF/LBR | Low-battery monitor outputs | LBO: open-drain fault flag; LBF: falling-edge interrupt; LBR: rising-edge interrupt - enables precise battery state tracking |
| RSO/MR | Reset control | RSO: active-low reset output; MR: manual reset input with 1µs minimum pulse width |
Key Features
| Feature | Design Value |
|---|---|
| Four synchronous step-down converters | REG1–REG4 deliver up to 1.6A total with 2MHz switching, enabling <5mm² total passive area per rail |
| I²C-based dynamic voltage management | Real-time adjustment of V3/V4 output voltages via register writes (e.g., 0x20), reducing processor active power by adaptive scaling |
| Always-on 3.3V/30mA LDO (REG8) | Independent V8 rail powered from IN8 ensures RTC, backup registers, and wake-up circuitry remain active during full system sleep |
| Integrated low-battery detection | LBO/LBF/LBR outputs provide hysteresis-controlled (±25mV) battery monitoring without external comparators or resistive dividers |
| Forced-PWM mode | Eliminates audible switching noise across full load range while maintaining tight output regulation (±1.5%) |
Applications
| Smart Cellular Phones | PDAs and Palmtops |
|---|---|
Use Scenario: Powering Marvell PXA300/PXA310 application processors with dynamic core voltage scaling during voice call, web browsing, and video playback. IC Role / Device Role / Timing Role: Primary PMIC managing all processor domain rails (VCC_IO, VCC_MEM, VCC_APPS, VCC_SRAM) and peripheral supplies (VCC_CARD1/2, VCC_MVT). Use Value: Reduces average system power by 22% via DVM-enabled V3/V4 voltage reduction during idle states, extending talk time by >18 minutes per charge. | Use Scenario: Supplying dual-core ARM-based PDA platforms requiring sequenced power-up of CPU, memory, display, and SD card interfaces. IC Role / Device Role / Timing Role: Central power sequencer coordinating 8-rail startup timing (tPHLVTH3 = 400µs, tSEHVMH = 290µs) and fault-safe shutdown. Use Value: Eliminates need for discrete sequencing ICs and external reset supervisors, reducing BOM count by 3 components and PCB area by 12mm². |
| Personal Media Players | Digital Cameras |
Use Scenario: Delivering clean, low-noise power to audio codecs, NAND flash, and LCD controllers in portable music/video players. IC Role / Device Role / Timing Role: Low-noise LDOs (REG5, REG6/REG7) supply analog audio paths and digital I/O, while forced-PWM mode suppresses EMI during recording. Use Value: Achieves <160µVRMS output noise on REG5, enabling SNR >95dB in headphone amplifiers without additional filtering. | Use Scenario: Powering CMOS image sensor, ISP, and SD card in compact digital cameras with rapid on/off cycling. IC Role / Device Role / Timing Role: Fast-enable LDOs (V5/V6/V7 ramp rates: 5–9 mV/µs) and quick-turn-on DC-DCs (V3/V4 enable time: 400µs) minimize boot latency to <120ms. Use Value: Enables sub-100ms wake-from-sleep shutter response, meeting consumer expectation for instant photo capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8661ETL+ | Omits REG1 (V1) and REG7 (V7); same 40-pin QFN, I²C interface, and DVM capability for V3/V4 | Targeted at simpler APs requiring only three DC-DCs (e.g., single-core PXA270), not quad-rail systems like PXA3xx | Select MAX8661ETL+ only when V1 and V7 rails are unused - saves cost but requires board redesign if later adding I/O or card power |
| TPS65023RGZR | Three DC-DCs (1.8A/1.2A/1.2A), six LDOs, no DVM; 48-pin QFN; 2.7–5.5V input; I²C-compatible but no V3/V4 dynamic scaling registers | Designed for OMAP-L137/DM365, lacks Marvell-specific DVM timing and voltage codes (e.g., Table 11 serial codes) | Choose TPS65023RGZR for TI-based designs needing higher current on VDD1/VDD2, but avoid for PXA3xx where DVM-driven power savings are mandatory |
Compared with MAX8661ETL+, MAX8660ETL+C7J provides full quad-DC-DC capability essential for Marvell PXA3xx's VCC_IO/VCC_MEM/VCC_APPS/VCC_SRAM domains; versus TPS65023RGZR, it delivers proven DVM firmware integration and tighter voltage accuracy (±1.5% for V3/V4) critical for processor stability under dynamic workloads.
Availability
MAX8660ETL+C7J is available at Aetrix Electronics and suitable for smart cellular phones, PDAs, and personal media players requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for MAX8660ETL+C7J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management solutions for portable, industrial, and communications applications.
The MAX8660 product line was engineered specifically to meet Marvell PXA3xx processor family power requirements - delivering tightly coupled DVM, ultra-low quiescent current, and integrated battery monitoring in a space-constrained 40-pin QFN.
FAQ
What is the default output voltage of the V3 rail on the MAX8660ETL+C7J?
The default output voltage of the V3 rail on the MAX8660ETL+C7J is 1.400V, as specified in the Electrical Characteristics table for REG3 under "MAX8660/MAX8660A/MAX86601 default output voltage". This value is factory-trimmed and applies when no I²C programming has been performed to modify the DVM register (0x20). The MAX8660ETL+C7J supports reprogramming V3 between 0.725V and 1.8V in real time via its I²C interface.
Does the MAX8660ETL+C7J support forced-PWM mode across all DC-DC converters?
Yes, the MAX8660ETL+C7J supports forced-PWM mode on all four synchronous step-down converters (REG1–REG4). This mode disables automatic pulse-skipping, ensuring constant 2MHz switching frequency regardless of load - critical for noise-sensitive applications like audio playback or RF sections. Forced-PWM is enabled per converter via dedicated I²C control bits and maintains ±1.5% output voltage accuracy even at light loads.
How does the MAX8660ETL+C7J handle low-battery conditions?
The MAX8660ETL+C7J uses a dedicated low-battery detector with three outputs: LBO (open-drain flag), LBF (falling-edge interrupt), and LBR (rising-edge interrupt). It asserts LBO when the monitored battery voltage falls below 1.200V (±18mV), with 49mV hysteresis (VLBRTH = 1.250V). The detector operates independently of main input voltage and draws <0.5nA bias current, enabling accurate fuel-gauge interfacing without loading the battery.
What is the purpose of the RAMP pin on the MAX8660ETL+C7J?
The RAMP pin on the MAX8660ETL+C7J sets the soft-start and dynamic voltage-change ramp rates for REG3 (V3) and REG4 (V4) outputs. Connecting a 56kΩ resistor from RAMP to a reference voltage (1.4V for MAX8660/MAX8660A/MAX86601, 1.15V for MAX8660B) configures the ramp rate to 8 mV/µs for soft-start and 10 mV/µs for dynamic changes. This prevents inrush current and ensures glitch-free voltage transitions during DVM events.
Can the MAX8660ETL+C7J power both VCC_CARD1 and VCC_CARD2 simultaneously at 3.3V?
Yes, the MAX8660ETL+C7J can power both VCC_CARD1 (REG6) and VCC_CARD2 (REG7) simultaneously at 3.3V. Each LDO supports 1.8–3.3V output in 0.1V steps and delivers up to 500mA. At 3.3V and 300mA load, dropout is specified at 100mV maximum, allowing operation from a 3.6V input. Both rails share the same IN67 input and are independently controllable via I²C, enabling staggered enable/disable for SDIO and MMC interfaces.
MAX8660ETL+C7J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Applications:
- -
- Current - Supply:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
MAX8660ETL+C7J FAQ
1.How can I place an order for MAX8660ETL+C7J through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8660ETL+C7J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8660ETL+C7J reliable?
The price and inventory of MAX8660ETL+C7J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8660ETL+C7J is usually 5 days.
3.What payment methods are accepted for MAX8660ETL+C7J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8660ETL+C7J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8660ETL+C7J?
MAX8660ETL+C7J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8660ETL+C7J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8660ETL+C7J?
For technical support, including MAX8660ETL+C7J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8660ETL+C7J requirements.
6.How does Aetrix verify that MAX8660ETL+C7J is sourced from the original manufacturer or authorized distributors?
All MAX8660ETL+C7J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8660ETL+C7J meets industry standards.
7.What is the process for return or replacement of MAX8660ETL+C7J?
All MAX8660ETL+C7J units undergo pre-shipment inspection (PSI). If there is an issue with MAX8660ETL+C7J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8660ETL+C7J part is unused and in its original packaging.
Return procedure for MAX8660ETL+C7J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX8660ETL+C7J Tags
-
TPS2511DGNR
Texas Instruments
-
UTC2000/MG
Microchip Technology
-
TUSB320HAIRWBR
Texas Instruments
-
TPS61252DSGR
Texas Instruments
-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments
-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments
-
STUSB1600AQTR
STMicroelectronics
-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments
-
TPS65150PWPR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
