Analog Devices Inc./Maxim Integrated MAXQ1062ETP+

Overview

MAXQ1062ETP+ from Maxim Integrated is a DeepCover® cryptographic controller IC designed as a secure coprocessor for embedded systems, providing hardware-accelerated TLS/DTLS key negotiation, ECDSA authentication, AES-128/-256 encryption (ECB/CBC/CCM/GCM), SHA-256/384/512 hashing, and true random number generation. It features 8KB of secure EEPROM for certificates, keys, and monotonic counters, and communicates via SPI or I²C in industrial temperature range (–40°C to +109°C).

For engineers reviewing the MAXQ1062ETP+ datasheet, MAXQ1062ETP+ pinout, MAXQ1062ETP+ application, or MAXQ1062ETP+ equivalent, this device delivers FIPS- and Common Criteria EAL4+-aligned security for IoT edge nodes, smart meters, PLCs, and gateways requiring certified key storage, secure boot, tamper detection, and offloaded TLS record processing without host firmware development.

Technical Context

The MAXQ1062ETP+ implements two distinct operational modes: TLS/DTLS toolbox mode for full protocol offload (including ECDHE, ECDSA, certificate chain validation, and master secret export), and AES-SPI mode for high-speed stream encryption (up to 20Mb/s) using dedicated hardware AES-GCM/ECB with DMA-linked SPI interface. Its dual-mode architecture isolates sensitive operations from the host while enabling flexible integration.

Security enforcement relies on physical tamper detection (voltage, frequency, temperature, light), life cycle management with one-way state transitions, secure file system access control per object, and immutable key storage-where private keys are never exposed in plaintext and require internal generation or cryptographically verified import. The true RNG feeds all key derivation and nonces.

Key Specifications

Pinout & Package

MAXQ1062ETP+ is housed in a 20-pin TQFN package (4mm × 4mm, 0.5mm pitch) with wettable flanks, optimized for space-constrained industrial PCB layouts and reflow compatibility.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar cryptographic coprocessor applications.

Compared with ATECC608A-TFLXT and SE050N-A110, the MAXQ1062ETP+ uniquely integrates TLS/DTLS offload with hardware-accelerated AES-SPI streaming, secure boot verification, and tamper-aware life cycle management-making it optimal for resource-constrained industrial devices requiring certified, end-to-end protocol security without host firmware development.

Availability

MAXQ1062ETP+ is available at Aetrix Electronics and suitable for smart metering, industrial PLCs, IoT edge gateways, and secure access control systems requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MAXQ1062ETP+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs high-performance analog and mixed-signal ICs for industrial, automotive, and computing applications, with emphasis on reliability, precision, and security.

The MAXQ1062ETP+ belongs to the DeepCover® cryptographic controller product line, engineered specifically to provide certified, hardware-enforced security for embedded devices where firmware-based crypto is impractical or insufficiently robust.

FAQ

What communication interfaces does the MAXQ1062ETP+ support?

The MAXQ1062ETP+ supports both I²C and SPI interfaces. I²C operates in slave mode at up to 400kbit/s (fast mode) with a default address of 0x60, configurable via software. SPI operates in slave mode using Mode 0 timing, LSB-first data order, and active-low SSEL. The SPI interface also enables AES-SPI mode for high-speed hardware encryption. Both interfaces are fully supported in the MAXQ1062ETP+'s TLS/DTLS and secure storage functions.

How does the MAXQ1062ETP+ handle secure key storage and access control?

The MAXQ1062ETP+ provides 8KB of secure EEPROM with atomic write capability and integrity protection. Keys and certificates are stored in a flexible file system where each object has user-programmable access conditions-such as requiring authentication, specific life cycle state, or tamper status. Private keys are never readable in plaintext and must be generated internally or imported only after successful signature verification using a pre-stored public key. This enforcement is implemented in hardware within the MAXQ1062ETP+.

Does the MAXQ1062ETP+ support TLS 1.2 and DTLS 1.2 protocols?

Yes, the MAXQ1062ETP+ supports TLS 1.2 and DTLS 1.2 in client mode. Its TLS/DTLS cryptographic toolbox handles full key negotiation (ECDH, ECDHE, PSK), ECDSA-based authentication, certificate chain validation, and master secret export. The MAXQ1062ETP+ performs all sensitive operations-including private key use and session key derivation-internally, ensuring no exposure to the host processor. It integrates with Arm Mbed TLS for host stack compatibility.

What tamper detection mechanisms are built into the MAXQ1062ETP+?

The MAXQ1062ETP+ includes multiple independent tamper detection features: voltage glitch monitoring, frequency deviation detection, temperature threshold sensing, and optical intrusion detection. Each can be individually enabled and configured to assert the open-drain RESET_OUT signal upon violation. These mechanisms are hardened at the silicon level and aligned with Common Criteria EAL4+ requirements. Tamper response behavior-including whether to erase keys or trigger reset-is configurable per the MAXQ1062ETP+'s life cycle state.

Can the MAXQ1062ETP+ function as a secure bootloader for an external microcontroller?

Yes, the MAXQ1062ETP+ supports secure boot functionality by verifying the integrity and authenticity of external MCU firmware images using SHA-256 hashing and ECDSA signature verification. Upon successful validation, the MAXQ1062ETP+ releases access to protected resources (e.g., keys or configuration objects). This capability is implemented in hardware and enforced through the MAXQ1062ETP+'s life cycle management and secure file system, ensuring that only cryptographically signed and trusted code executes.