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Analog Devices Inc./Maxim Integrated MAXQ1065GTC+
- Part No.:
- MAXQ1065GTC+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Application Specific Microcontrollers
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
MAXQ1065GTC+.pdf
- Description:
- DEEPCOVER CRYPTO CONTROLLER T&R
- Quantity:
- Payment:
- Shipping:
Inventory:388
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Product details
Overview
MAXQ1065GTC+ from Analog Devices is an ultra-low-power cryptographic controller implementing ChipDNA® PUF-based secure key storage, ECC NIST P-256, SHA-256, AES-128/192/256, and full TLS 1.2 client-side support - deployed as a hardware root-of-trust in medical wearables and industrial IoT edge nodes requiring tamper-resistant secure boot and firmware update.
For engineers reviewing the MAXQ1065GTC+ datasheet, MAXQ1065GTC+ pinout, MAXQ1065GTC+ application, or MAXQ1065GTC+ equivalent, this page delivers verified electrical specs (1.62V–3.63V, -40°C to +105°C), interface timing (10MHz SPI / 1Mbps I²C), power states (100nA standby), tamper response behavior, and secure storage access control model - all confirmed against Analog Devices' official documentation.
Technical Context
The MAXQ1065GTC+ integrates three independent crypto engines - ECC (secp256r1), SHA-2, and AES - with on-chip TRNG compliant to NIST SP800-90A/B/C and deterministic key derivation per SP800-56Ar3. Its life cycle management enforces stage-specific access rules for keys, certificates, and counters across provisioning, deployment, and decommissioning phases.
It supports dual-interface operation: 10MHz SPI (Mode 0/3) with RDY handshake and 100kbps/1Mbps I²C with configurable pull-ups; both interfaces enable secure channel establishment using preshared keys or ECDH. The TAMPER_IN pin triggers user-defined zeroization, while RESET_OUT provides open-drain event-driven reset signaling to host MCUs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.62V to 3.63V - enables direct integration with 1.8V/3.3V host MCU rails without level-shifting. |
| Operating Temperature | -40°C to +105°C - qualified for long-term deployment in harsh industrial and medical environments. |
| Standby Current | 100nA (typ) - extends battery life in wearable and remote sensor applications. |
| Secure Storage | 8KB flash with ChipDNA® PUF encryption - prevents physical extraction of keys even with die-level probing. |
| SPI Speed | 10MHz - supports high-throughput certificate exchange and bulk encrypted data transfer. |
| I²C Speed | 1Mbps - allows fast provisioning and configuration in space-constrained designs where SPI routing is impractical. |
| Tamper Response | Configurable zeroization on TAMPER_IN assertion - ensures sensitive assets are erased before physical compromise completes. |
Pinout & Package
MAXQ1065GTC+ uses a 12-pin, 3mm × 3mm TDFN-EP package with exposed pad soldered to ground plane for thermal and EMI performance. Pin functions differ between SPI and I²C variants; this part supports both configurations via pin mapping.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply input | Must be bypassed with 4.7μF + 0.1μF capacitors; powers all crypto engines and secure storage. |
| GND | Digital ground reference | Direct connection to PCB ground plane required; shared with exposed pad for low-impedance return path. |
| PDWN | Power-down control | Pulling low erases volatile registers and enters ultra-low-power state; must be high during crypto operations. |
| TAMPER_IN | Active-low tamper detection input | Triggers configurable zeroization when driven low; weak internal pull-up enables floating default state. |
| RDY | Ready status output | Open-drain signal indicating command processing completion or readiness for next SPI/I²C transaction. |
| SPIS_SCK / SCL | Clock input (SPI) or bidirectional clock (I²C) | 10MHz max for SPI; 1MHz max for I²C - defines host communication bandwidth and latency budget. |
| SPIS_MISO / SDA | Data output (SPI) or bidirectional data (I²C) | Drives MISO at VDD–0.4V min; SDA requires external 2.7kΩ pull-up for I²C compliance. |
| CEXT | External capacitor connection | Connects to 1μF ceramic cap to ground - stabilizes internal LDO and ensures reliable TRNG entropy generation. |
Key Features
| Feature | Design Value |
|---|---|
| ECC Compute Engine (NIST P-256) | Enables ECDSA signatures, ECDHE key exchange, and certificate verification without exposing private keys to host MCU. |
| ChipDNA® PUF Encryption | Generates device-unique, unclonable cryptographic keys bound to silicon - eliminates need for external key injection or secure programming facilities. |
| TLS 1.2 Full Stack Support | Offloads entire TLS record layer (AES-GCM/CCM) and handshake (PSK/ECDHE) - host MCU avoids storing secrets or implementing complex protocol logic. |
| Life Cycle Management | Enforces read/write permissions per stage (e.g., lock certificate updates after deployment) - aligns security policy with product manufacturing and field service workflows. |
| Secure Channel over SPI/I²C | Encrypts and authenticates all host commands/responses using session keys derived from ECDH or PSK - prevents bus snooping and replay attacks. |
Applications
| Medical Wearables | Industrial IoT Gateways |
|---|---|
Use Scenario: Continuous glucose monitor transmitting encrypted biometric data to cloud via BLE gateway. IC Role / Device Role / Timing Role: Hardware root-of-trust performing ECDSA authentication, AES-GCM encryption, and secure boot validation of sensor firmware. Use Value: Prevents unauthorized firmware modification and ensures end-to-end data confidentiality without burdening the ultra-low-power BLE SoC. | Use Scenario: Programmable logic controller (PLC) in oil refinery SCADA network requiring authenticated firmware updates over cellular backhaul. IC Role / Device Role / Timing Role: Secure bootloader and TLS 1.2 client managing certificate chain verification, ECDHE key exchange, and AES-CCM packet encryption. Use Value: Enables zero-touch remote updates with cryptographic integrity assurance - eliminating manual field visits for firmware patches. |
| Smart Metering | Building Automation Controllers |
Use Scenario: Electricity meter transmitting usage data to utility AMI infrastructure using DLMS/COSEM over IPv6. IC Role / Device Role / Timing Role: X.509 certificate manager and TLS endpoint verifying utility server identity and encrypting payload with AES-128-GCM. Use Value: Meets IEC 62056-47 and NISTIR 7628 security requirements for grid-edge devices with minimal host MCU resource overhead. | Use Scenario: HVAC controller in commercial building integrating with BACnet/IP network and cloud-based energy management platform. IC Role / Device Role / Timing Role: Mutual authentication engine validating both BACnet server and cloud API credentials using stored root and device certificates. Use Value: Enforces strict access control across multi-vendor systems - preventing unauthorized reconfiguration or data exfiltration via compromised endpoints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar cryptographic controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATECC608A-TFLXT | Supports ECC P-256 and SHA-256 but lacks native TLS stack; relies on host MCU for record-layer encryption and handshake logic. | Better suited for cost-sensitive consumer IoT where host handles TLS protocol; not ideal for resource-constrained medical or industrial hosts. | Select ATECC608A-TFLXT only if host MCU has sufficient RAM/CPU to implement TLS and secure channel logic. |
| SE050T1A | Includes JavaCard OS and supports ISO 7816-4 APDU interface; offers broader algorithm support (RSA-2048, SM2) but higher power (2.5µA standby vs. 100nA). | Targeted at payment terminals and eID cards requiring smart card interoperability; less optimized for embedded sensor node integration. | Choose SE050T1A when ISO-compliant secure element functionality or RSA-based PKI is mandatory, not for ultra-low-power edge nodes. |
Compared with ATECC608A-TFLXT and SE050T1A, MAXQ1065GTC+ uniquely combines sub-µA standby current, integrated TLS 1.2 offload, and ChipDNA® PUF in a 3mm × 3mm footprint - making it the only option certified for long-life medical wearables and industrial gateways requiring zero-trust boot and field-updatable crypto agility.
Availability
MAXQ1065GTC+ is available at Aetrix Electronics and suitable for medical wearables, industrial IoT gateways, and smart metering applications requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for MAXQ1065GTC+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The MAXQ1065GTC+ belongs to Analog Devices' DeepCover® embedded security portfolio, designed specifically to provide hardware-enforced root-of-trust for battery-powered and space-constrained edge devices in regulated environments.
FAQ
What cryptographic algorithms does the MAXQ1065GTC+ support natively?
The MAXQ1065GTC+ supports ECC NIST P-256 (secp256r1) for ECDSA and ECDHE, SHA-256, AES-128/192/256 in ECB/CBC/CCM/GCM modes, HMAC-SHA-256, AES-CBC-MAC, AES-CMAC, and NIST SP800-90A/B/C-compliant TRNG. All operations execute within the secure boundary - no algorithm code or keys ever leave the MAXQ1065GTC+ die.
How does the ChipDNA® PUF technology enhance security in the MAXQ1065GTC+?
ChipDNA® PUF in the MAXQ1065GTC+ generates device-unique cryptographic keys from inherent silicon variations - keys that cannot be extracted, cloned, or predicted. Even if the MAXQ1065GTC+ die is physically probed, the PUF-derived keys remain unrecoverable, ensuring secure key storage without external provisioning infrastructure.
Can the MAXQ1065GTC+ operate as a standalone TLS endpoint without host MCU involvement?
No - the MAXQ1065GTC+ acts as a cryptographic co-processor, not a full network stack. It performs TLS 1.2 handshake and record-layer operations (ECDHE, ECDSA, AES-GCM), but requires a host MCU to manage TCP/IP, socket handling, and application-layer data flow. The MAXQ1065GTC+ offloads only the security-critical portions.
What is the function of the TAMPER_IN pin on the MAXQ1065GTC+?
The TAMPER_IN pin on the MAXQ1065GTC+ is an active-low input that triggers configurable security responses - such as zeroization of secret keys or assertion of RESET_OUT - when driven low by an external tamper sensor. By default, it's disabled and may be left unconnected unless system-level intrusion detection is required.
Does the MAXQ1065GTC+ support both SPI and I²C interfaces simultaneously?
No - the MAXQ1065GTC+ supports either SPI or I²C, determined by hardware configuration at power-on. Pin assignments differ between MAXQ1065-SPI and MAXQ1065-I²C variants; the GTC+ suffix denotes the 12-pin TDFN package compatible with both interface modes via appropriate pin strapping and layout design.
MAXQ1065GTC+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Security
- Core Processor:
- MAXQ
- Program Memory Type:
- FLASH (8kB)
- Controller Series:
- MAXQ™
- RAM Size:
- -
- Interface:
- I2C, SPI
- Number of I/O:
- -
- Voltage - Supply:
- 1.62V ~ 3.63V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-TDFN (3x3)
MAXQ1065GTC+ FAQ
1.How can I place an order for MAXQ1065GTC+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAXQ1065GTC+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAXQ1065GTC+ reliable?
The price and inventory of MAXQ1065GTC+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAXQ1065GTC+ is usually 5 days.
3.What payment methods are accepted for MAXQ1065GTC+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAXQ1065GTC+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAXQ1065GTC+?
MAXQ1065GTC+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAXQ1065GTC+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAXQ1065GTC+?
For technical support, including MAXQ1065GTC+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAXQ1065GTC+ requirements.
6.How does Aetrix verify that MAXQ1065GTC+ is sourced from the original manufacturer or authorized distributors?
All MAXQ1065GTC+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAXQ1065GTC+ meets industry standards.
7.What is the process for return or replacement of MAXQ1065GTC+?
All MAXQ1065GTC+ units undergo pre-shipment inspection (PSI). If there is an issue with MAXQ1065GTC+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAXQ1065GTC+ part is unused and in its original packaging.
Return procedure for MAXQ1065GTC+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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