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NXP Semiconductors MC13892DJVLR2
- Part No.:
- MC13892DJVLR2
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 186-LFBGA
- Datasheet:
-
MC13892DJVLR2.pdf
- Description:
- IC PWR MGMT I.MX35/51 186BGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,551
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Product details
Overview
MC13892DJVLR2 from NXP Semiconductors (formerly Freescale) is a highly integrated Power Management IC designed specifically for i.MX35 and i.MX51 application processors, featuring four adjustable buck regulators (up to 1050 mA), twelve LDOs, a 300 mA boost regulator, 10-bit ADC with coulomb counter, RTC with coin-cell backup, touch screen interface, and SPI/I²C control. It powers netbooks, smart mobile devices, and portable navigation systems.
For engineers reviewing the MC13892DJVLR2 datasheet, MC13892DJVLR2 pinout, MC13892DJVLR2 application, or MC13892DJVLR2 equivalent, key selection criteria include its 139-pin 7×7 mm BGA package, default-OFF global reset function, support for Li-ion battery charging with USB/wall input, and compatibility with i.MX27/31/37/51 processor families.
Technical Context
The MC13892DJVLR2 implements SMARTMOS technology with dedicated power rails for processor core (VCORE), digital core (VCOREDIG), memory (VSD), audio (VAUDIO), video (VVIDEO), camera (VCAM), and high-voltage I/O (VIOHI). Its power control logic includes programmable startup sequencing, dynamic voltage scaling inputs (DVS1/DVS2), and multiple standby modes (ON Standby: 230–295 µA; OFF Mode: 10–30 µA).
It integrates a 32.768 kHz crystal oscillator with RTC block, supports external 32 kHz clock input via CLK32KMCU, and provides real-time battery monitoring via BATTISNS, CHRGISNS, and BATTISNSCC pins. The coulomb counter uses CFP/CFM filter pins and interfaces with the 10-bit ADC for precise charge accumulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Regulators | 4 adjustable: SW1 (1050 mA), SW2–SW4 (800 mA each); output range 0.6–1.85 V; ±50 mV accuracy in PWM mode |
| LDO Count | 12 adjustable LDOs with internal/external pass devices; supports mixed analog/digital rail generation |
| Boost Regulator | 300 mA output (SWBSTOUT); supplies RGB LEDs up to 28 V sink capability |
| ADC & Coulomb Counter | 10-bit general-purpose ADC with 7 channels (ADIN5–ADIN7, etc.); integrated coulomb counter with CFP/CFM filtering |
| RTC & Oscillator | On-chip 32.768 kHz crystal oscillator; VSRTC output (1.15–1.25 V); coin-cell backup (LICELL, 1.8–3.6 V) |
| Interface | SPI primary interface (CS/MOSI/MISO/CLK); optional I²C mode; interrupt-driven register access |
| Package | 139-pin 7×7 mm BGA (VK suffix); thermal resistance RθJA = 104 °C/W (single-layer board) |
Pinout & Package
MC13892DJVLR2 is housed in a 139-pin, 7×7 mm BGA package (VK suffix) with 0.5 mm pitch. Pin assignments follow the MC13892VK layout per Figure 3 and Table 2 of Rev. 19.0 datasheet. Grounding uses nine dedicated substrate grounds (GNDSUB1–GNDSUB9) plus functional grounds (GNDSW1–GNDSW4, GNDBL, GNDLED, etc.) for noise isolation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A2, B1 | VUSB2 | 3.6 V output regulator for USB PHY; powered from BP input |
| A4 | SWBSTIN | 5.5 V input to 300 mA boost switcher; connects to BP or external supply |
| A9 | VCORE | 3.6 V regulated analog core supply; powers internal analog blocks |
| B9 | VCOREDIG | 1.5 V digital core supply; powers internal logic and SPI interface |
| D1 | VUSB | 3.6 V USB transceiver regulator; supports OTG detection via UVBUS |
| F11 | RESETBMCU | Open-drain MCU reset output; requires external pull-up to VCOREDIG |
| H2 | MISO | SPI read data output; CMOS level referenced to SPIVCC (1.75–3.1 V) |
| J2 | MOSI | SPI write data input; weak pull-down enables I²C fallback at boot |
| K2 | SPIVCC | 3.6 V supply input for SPI bus; typically sourced from SW4 buck output |
| N5–N6 | XTAL1/XTAL2 | 32.768 kHz crystal connections; enable RTC and low-power timing |
Key Features
| Feature | Design Value |
|---|---|
| Battery charger system | Supports wall adapter and USB charging paths with dual FET control (CHRGCTRL1/CHRGCTRL2), trickle LED drive (CHRGLED), and SE1 detection (CHRGSE1B) |
| Four-buck + twelve-LDO architecture | Enables independent voltage scaling for i.MX processor domains: core (SW1), memory (SW2), peripherals (SW3/SW4), and mixed-signal (VIOHI, VAUDIO, VVIDEO) |
| Integrated touch screen interface | Four-wire resistive touchscreen support via TSX1/TSX2/TSY1/TSY2 and reference output (TSREF); eliminates external controller |
| Real-time clock with backup | Hardware RTC with 32 kHz oscillator, VSRTC output (1.2 V ±25 mV), and coin-cell backup (LICELL) with 1.8–3.6 V operating range |
| Programmable power sequencing | Startup sequencer controlled by PUMS1/PUMS2 inputs; supports cold-start configuration and multi-rail enable timing |
| Low-power operation modes | OFF mode (10–30 µA), RTC-only mode (3–6 µA), and ON Standby (230–295 µA) enable extended battery life in portable devices |
Applications
| Smartphone Power Management | Portable Navigation Device (PND) |
|---|---|
Use Scenario: Compact smartphone using i.MX51 processor with multi-rail power demands, Li-ion battery, RGB display backlight, and capacitive/touchscreen UI. IC Role / Device Role / Timing Role: Central PMIC managing all DC-DC conversion, battery charging, RTC, touchscreen interface, and peripheral power sequencing. Use Value: Reduces BOM count by integrating 4 bucks, 12 LDOs, boost, ADC, RTC, and touchscreen drivers - eliminating ≥8 discrete regulators and 2 interface ICs. | Use Scenario: Automotive-grade PND requiring robust power control, GPS module supply, SD card interface (VSD), and video output (VVIDEO) for map rendering. IC Role / Device Role / Timing Role: Primary power controller delivering stable 1.5 V (VCOREDIG), 3.3 V (VIOHI), 2.8 V (VSD), and 3.6 V (VAUDIO) rails while supporting cold-start via PWRON1/PWRON2 buttons. Use Value: Enables single-chip power solution with integrated VSD regulator (3.6 V @ 300 mA) and VVIDEO (3.6 V) - avoiding external LDOs for SD and TV DAC supplies. |
| eBook Reader System | Industrial Handheld Terminal |
Use Scenario: E-ink eBook reader based on i.MX35 with ultra-low standby current, frontlight control, and long battery life. IC Role / Device Role / Timing Role: Low-quiescent PMIC providing ON Standby (230–295 µA) and OFF (10–30 µA) modes, plus programmable backlight dimming via LEDKP/LEDMD drivers. Use Value: Achieves >30-day standby via RTC-only mode (3–6 µA) and coin-cell backup - sustaining calendar/time without main battery. | Use Scenario: Rugged handheld terminal with barcode scanner, Wi-Fi/BT module (VPLL), audio codec (VAUDIO), and keypad illumination (LEDKP). IC Role / Device Role / Timing Role: Multi-rail power hub supplying VPLL (3.6 V), VAUDIO (3.6 V), VIOHI (3.6 V), and keypad LED sink (LEDKP, 28 V capable). Use Value: Delivers 28 V sink capability on LEDKP pin for high-brightness keypad lighting - eliminating external LED driver ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC34708VLHR2 | 186-pin 12×12 mm BGA; higher pin count; supports i.MX53/i.MX6; no coulomb counter; different DVS mapping | Targeted at newer i.MX6 platforms; lacks integrated coulomb counter and TS interface; requires external RTC | Select when upgrading to i.MX6 and needing higher integration density, not for i.MX35/51 drop-in replacement |
| PF0100AZES | NXP PF0100: 139-pin 7×7 mm BGA; pin-compatible with MC13892; supports i.MX6SoloLite; adds USB OTG PHY support | Designed for i.MX6 family; retains same buck/LDO count but adds USB PHY and enhanced thermal monitoring | Use for i.MX6 designs where footprint compatibility matters; not validated for i.MX35/51 software stack |
Compared with MC34708VLHR2 and PF0100AZES, the MC13892DJVLR2 offers unique coulomb counting, integrated touchscreen interface, and i.MX35/51-optimized register map - making it irreplaceable in legacy netbook and ebook designs requiring battery fuel gauging and resistive touch support.
Availability
MC13892DJVLR2 is available at Aetrix Electronics and suitable for smartphone power subsystems, portable navigation devices, eBook readers, and industrial handheld terminals requiring stable component supply across extended product lifecycles.
Supply support for MC13892DJVLR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications.
The MC13892DJVLR2 belongs to NXP's legacy i.MX companion PMIC product line, engineered to deliver complete, application-processor-specific power and user-interface management for Freescale-origin i.MX3x/5x platforms.
FAQ
What is the package type and pin count of the MC13892DJVLR2?
The MC13892DJVLR2 uses a 139-pin, 7×7 mm body-size BGA package with 0.5 mm pitch (VK suffix). This matches the MC13892CJVK and MC13892BJVK variants and is distinct from the 186-pin VL package. Pin layout follows Figure 3 and Table 2 in Rev. 19.0 datasheet.
Does the MC13892DJVLR2 support both USB and wall adapter battery charging?
Yes, the MC13892DJVLR2 supports dual-input battery charging via dedicated CHRGCTRL1/CHRGCTRL2 outputs driving external FETs, with separate CHRGRAW input for charger sensing. It handles USB (VBUS/UVBUS) and wall adapter (BP) sources, including SE1 detection (CHRGSE1B) and trickle-charge LED drive (CHRGLED).
What is the function of the MODE pin on the MC13892DJVLR2?
The MODE pin (A8) on the MC13892DJVLR2 selects operational mode: USB LBP, normal, or test mode. It accepts 0–9.0 V and is latched during cold start. Unlike other pins, it has no ESD protection and must be driven within its rated voltage range to avoid damage.
How does the MC13892DJVLR2 implement real-time clock functionality?
The MC13892DJVLR2 integrates a 32.768 kHz crystal oscillator with dedicated XTAL1/XTAL2 pins, VSRTC output (1.15–1.25 V), and GNDRTC ground. It supports coin-cell backup via LICELL (1.8–3.6 V) and maintains time in OFF mode (3–6 µA) - enabling calendar persistence without main battery power.
Is the MC13892DJVLR2 compatible with i.MX27 and i.MX37 processors?
Yes, the MC13892DJVLR2 is explicitly documented as compatible with i.MX27, i.MX31, i.MX37, i.MX35, and i.MX51 application processors. Its register map, power rail assignments (VCORE, VCOREDIG, VSD), and interface timing (SPI/I²C) are validated for all these families per Freescale's Device Variations table and Figure 1 typical operating circuit.
MC13892DJVLR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 186-LFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Battery Management, Display (LED Drivers), Handheld/Mobile Devices, Power Supply
- Current - Supply:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 186-PBGA (12x12)
MC13892DJVLR2 FAQ
1.How can I place an order for MC13892DJVLR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for MC13892DJVLR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MC13892DJVLR2 reliable?
The price and inventory of MC13892DJVLR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC13892DJVLR2 is usually 5 days.
3.What payment methods are accepted for MC13892DJVLR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC13892DJVLR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MC13892DJVLR2?
MC13892DJVLR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MC13892DJVLR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MC13892DJVLR2?
For technical support, including MC13892DJVLR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC13892DJVLR2 requirements.
6.How does Aetrix verify that MC13892DJVLR2 is sourced from the original manufacturer or authorized distributors?
All MC13892DJVLR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC13892DJVLR2 meets industry standards.
7.What is the process for return or replacement of MC13892DJVLR2?
All MC13892DJVLR2 units undergo pre-shipment inspection (PSI). If there is an issue with MC13892DJVLR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MC13892DJVLR2 part is unused and in its original packaging.
Return procedure for MC13892DJVLR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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