Microchip Technology MEC1310-NU
- Part No.:
- MEC1310-NU
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 128-TQFP
- Datasheet:
-
MEC1310-NU.pdf
- Description:
- IC EMBEDDED CTLR 128TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,238
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Product details
Overview
MEC1310-NU from Microchip Technology is a 128-pin VTQFP ACPI 2.0–compliant embedded controller for notebook PCs, integrating a high-performance 8051 core, 64KB executable SRAM, 1024B boot ROM, and dual fan tachometer/PWM control with ±3% RPM accuracy from 500–16k RPM. It supports LPC bus frequencies from 19.2MHz to 33MHz and delivers system power management via three ACPI EC interfaces and SCI/SMI signaling.
For engineers reviewing the MEC1310-NU datasheet, MEC1310-NU pinout, MEC1310-NU application, or MEC1310-NU equivalent, key selection criteria include LPC timing compliance, VCC0-backed register retention, 3.3V operation with 5V-tolerant PS/2 buffers, and hardware-accelerated RPM-based fan control requiring no host CPU intervention.
Technical Context
The MEC1310-NU implements a dual-power-plane architecture (VCC0/VCC1) enabling instant-on standby with battery-backed 64-byte registers and fail-safe 32.768kHz ring oscillator (±2% accuracy). Its 8051 core executes from internal SRAM loaded via HOST/8051 SPI interface supporting switched or parallel shared SPI flash configurations.
LPC interface compliance includes Clock Run support, Serial IRQ, 15 direct IRQs, ACPI SCI, nSMI output, and shadowed write-only registers. Three 8584-style I²C/SMBus controllers operate fully on standby power, each with dedicated pin sets-two controllers offer two selectable ports per controller, one offers one port.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19.2MHz to 33MHz - defines maximum host-to-EC communication bandwidth and timing margin for ACPI state transitions |
| Embedded SRAM | 64KB executable - provides full 8051 program space; 32KB shared with data space enables efficient code+data co-location |
| Fan Control Accuracy | ±3% from 500–16k RPM - enables precise thermal regulation without software calibration overhead |
| ADC Resolution | 10-bit, 5 channels - delivers 25.78mV LSB resolution over 0–3.3V range; Channel 0 accepts 5V-tolerant input |
| PS/2 Ports | Four independent hardware-driven - each with GPIO association enables simultaneous keyboard/mouse/touchpad/trackpoint support |
| Wake-Up Events | 64 maskable hardware sources - allows selective low-power suspend with granular event-triggered resume (e.g., lid open, AC insert) |
| Debug Interface | 16550A-compatible UART with 16-byte FIFO - supports high-speed trace logging and firmware debugging without host resource contention |
Pinout & Package
MEC1310-NU is housed in a RoHS-compliant 128-pin VTQFP package (14×14×1.0 mm), with pin multiplexing supporting LPC, PS/2, I²C/SMBus, PECI, BC-Link, and GPIO functions as defined in Microchip DS00001768A.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Address/Data Bus | Time-multiplexed 4-bit bidirectional bus for configuration and data transfer with host south bridge |
| LFRAME# | LPC Frame Signal | Indicates start/end of LPC transaction cycle; synchronizes host and EC timing |
| LRESET# | LPC Reset Input | Asynchronous reset signal from host to initialize EC logic and registers |
| nEC_SCI | ACPI System Control Interrupt | Open-drain active-low interrupt to host for ACPI event notification (e.g., thermal trip, battery low) |
| VCC0 | Standby Power Supply | Provides always-on power to 64-byte battery-backed registers and RTC-related logic during S3/S4 sleep |
| 32KHZ_INPUT | External 32.768kHz Clock Input | Single-ended reference for fail-safe ring oscillator; enables RSMRST#-gated clock distribution in deep sleep |
Key Features
| Feature | Design Value |
|---|---|
| RPM-PWM Fan Control | Hardware block using one tachometer input + one PWM output enables closed-loop speed regulation without CPU polling or timer interrupts |
| VCC0-Backed Resources | 64-byte registers + status register retain state during VCC1 power loss, enabling fast resume from S3 and reliable wake-event tracking |
| Three I²C/SMBus Controllers | Two controllers support dual-port operation (AB1A/AB1B, AB2A/AB2B); third uses AB3 - all functional on standby power for sensor monitoring |
| BC-Link Bus Master | Combined high-speed/low-speed master controller enables direct peripheral access (e.g., touchpad, fingerprint) without host CPU involvement |
| PECI 2.0 Interface | Dedicated PECI_DAT and PECI_VREF pins provide native processor thermal telemetry and throttling coordination in modern Intel platforms |
Applications
| Thermal Management System | Notebook Platform Power Control |
|---|---|
Use Scenario: Real-time fan speed adjustment based on CPU/GPU die temperature readings from PECI and ADC channels. IC Role / Device Role / Timing Role: Embedded controller executing RPM-PWM algorithm with hardware tachometer feedback and 3% accuracy across 500–16k RPM range. Use Value: Eliminates host CPU polling overhead and ensures stable acoustic profile while maintaining safe junction temperatures under dynamic load. | Use Scenario: Coordinating S0ix/S3/S4 transitions, managing VCC0/VCC1 power planes, and asserting nSMI/nEC_SCI for OS-level power state changes. IC Role / Device Role / Timing Role: ACPI 2.0–compliant embedded controller providing SCI signaling, shadowed PM registers, and fast GATEA20/CPU_RESET assertion. Use Value: Enables sub-100ms resume from S3 and deterministic wake latency for lid-open or AC-insert events. |
| Multi-Device Peripheral Hub | Keyboard & Input Subsystem |
Use Scenario: Aggregating I²C sensor data (battery fuel gauge, ambient light, lid switch), BC-Link touchpad commands, and PECI thermal telemetry into unified host-facing LPC transactions. IC Role / Device Role / Timing Role: Peripheral hub with three independent I²C/SMBus controllers (six total ports), BC-Link master, and PECI 2.0 interface-all operational on VCC0 standby power. Use Value: Reduces host south bridge I/O loading and enables always-on sensor monitoring without waking main CPU. | Use Scenario: Scanning 18×8 keyboard matrix, decoding PS/2 keyboard/mouse protocols, and driving LED indicators (nBAT_LED, nPWR_LED). IC Role / Device Role / Timing Role: 8051-based keyboard controller with integrated KSI/KSO drivers, four hardware PS/2 ports, and LED driver outputs. Use Value: Offloads 8042-style host interface processing and supports simultaneous multi-input device operation with zero host interrupt latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar embedded controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IT8528E | Supports LPC up to 48MHz; lacks PECI 2.0; uses external 32.768kHz crystal instead of integrated ring oscillator | Targeted at mainstream desktop motherboards rather than thin-and-light notebooks requiring ultra-low standby current | Select when higher LPC bandwidth is required and PECI telemetry is not needed |
| W83L786NG | Legacy ISA-based design; no VCC0-backed registers; only two PS/2 ports; no BC-Link or PECI support | Suitable for cost-sensitive legacy industrial PC designs where ACPI 2.0 and fan RPM control are not required | Select only for brownfield designs with existing ISA Plug-and-Play infrastructure and no thermal management demands |
Compared with IT8528E and W83L786NG, the MEC1310-NU uniquely combines VCC0-backed state retention, hardware RPM-PWM control, PECI 2.0, and BC-Link-making it the only option for modern ultrabook platforms requiring coordinated thermal, power, and peripheral management without host CPU intervention.
Availability
MEC1310-NU is available at Aetrix Electronics and suitable for notebook thermal management systems, ACPI-compliant platform power control, and multi-peripheral embedded hub applications requiring stable component supply and long-term lifecycle support.
Supply support for MEC1310-NU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and embedded control solutions with global manufacturing and support infrastructure.
The MEC1310 product line delivers highly integrated, low-power embedded controllers optimized for Windows-compatible notebook PCs, emphasizing ACPI 2.0 compliance, hardware-accelerated thermal management, and seamless host-EC interoperability via LPC and PECI.
FAQ
What is the operating voltage range for the MEC1310-NU?
MEC1310-NU operates at 3.3V nominal supply (VCC1) with 5V-tolerant buffers on all PS/2 pins. It features dual power planes: VCC0 (standby) and VCC1 (main), enabling battery-backed register retention and low-current sleep modes. The 32.768kHz input accepts standard CMOS-level signals, and the internal ring oscillator requires no external crystal.
Does the MEC1310-NU support PECI 2.0 natively?
Yes, the MEC1310-NU includes dedicated PECI_DAT and PECI_VREF pins and implements full PECI 2.0 protocol support for processor thermal telemetry and throttling coordination. This capability is confirmed in DS00001768A-page 1 feature list and block diagram (Figure 1), enabling direct communication with Intel Core i-series and later CPUs without external level-shifting or protocol translation.
How many I²C/SMBus controllers does the MEC1310-NU integrate, and what are their capabilities?
The MEC1310-NU integrates three 8584-style I²C/SMBus controllers. Two support dual-port operation (AB1A/AB1B and AB2A/AB2B), and one uses AB3. All three operate fully on VCC0 standby power, allowing continuous sensor monitoring during system sleep. Each controller supports both master and slave modes under 8051 control, with configurable clock stretching and arbitration.
What fan control functionality is implemented in hardware within the MEC1310-NU?
The MEC1310-NU implements a dedicated RPM-PWM hardware block that pairs one tachometer input (FAN_TACH1/2) with one PWM output (PWM0–4) to deliver closed-loop fan speed control with ±3% accuracy from 500–16k RPM. It includes automatic spin-up, ramp rate control, aging/failure detection, and tachometer feedback-requiring no host CPU intervention or firmware polling loops.
Is the MEC1310-NU pin-compatible with other Microchip MEC family members?
No, the MEC1310-NU is not pin-compatible with earlier MEC devices such as MEC10xx or MEC11xx series. Its 128-pin VTQFP footprint, LPC signal mapping (LAD[3:0], LFRAME#, LRESET#), and dedicated PECI/BC-Link pins are unique to the MEC1310 family. Migration requires PCB layout revision and firmware adaptation due to differences in register map, power plane routing, and peripheral pin assignments.
MEC1310-NU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- I/O Controller
- Core Processor:
- 8051
- Program Memory Type:
- -
- Controller Series:
- -
- RAM Size:
- 64K x 8
- Interface:
- ACPI, BC-Link, I2C/SMBus, LPC, PECI, PS/2, SPI
- Number of I/O:
- 56
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 128-VTQFP (14x14)
MEC1310-NU FAQ
1.How can I place an order for MEC1310-NU through Aetrix?
Please submit a Request for Quotation (RFQ) for MEC1310-NU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MEC1310-NU reliable?
The price and inventory of MEC1310-NU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MEC1310-NU is usually 5 days.
3.What payment methods are accepted for MEC1310-NU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MEC1310-NU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MEC1310-NU?
MEC1310-NU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MEC1310-NU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MEC1310-NU?
For technical support, including MEC1310-NU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MEC1310-NU requirements.
6.How does Aetrix verify that MEC1310-NU is sourced from the original manufacturer or authorized distributors?
All MEC1310-NU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MEC1310-NU meets industry standards.
7.What is the process for return or replacement of MEC1310-NU?
All MEC1310-NU units undergo pre-shipment inspection (PSI). If there is an issue with MEC1310-NU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MEC1310-NU part is unused and in its original packaging.
Return procedure for MEC1310-NU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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