Microchip Technology MEC1310-NU-TR
- Part No.:
- MEC1310-NU-TR
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 128-TQFP
- Datasheet:
-
MEC1310-NU-TR.pdf
- Description:
- IC EMBEDDED CTLR 128TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,356
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MEC1310-NU-TR from Microchip Technology is a 128-pin VTQFP ACPI 2.0–compliant embedded controller IC for notebook PC I/O management, integrating an 8051 core, 64KB executable SRAM, 1024B boot ROM, 3× I²C/SMBus controllers, 4× PS/2 ports, PECI 2.0 interface, and hardware fan RPM control with ±3% accuracy from 500–16k RPM.
For engineers reviewing the MEC1310-NU-TR datasheet, MEC1310-NU-TR pinout, MEC1310-NU-TR application, or MEC1310-NU-TR equivalent, this device serves as a system-level keyboard and power management controller in Windows-compatible laptop platforms requiring LPC bus integration, battery-backed registers, and multi-rail power sequencing support.
Technical Context
The MEC1310-NU-TR implements a dual-power-plane architecture (VCC0/VCC1) enabling instant-on operation and low-standby-current sleep modes, with VCC0-backed 64-byte registers and integrated standby power reset generator (VCC1_RST# open-drain output). Its 8051 core executes from internal 64KB SRAM loaded via HOST/8051 SPI interface supporting switched or parallel shared flash configurations.
LPC interface compliance includes 19.2–33 MHz bus frequency support, Serial IRQ compatibility, 15 direct IRQs, ACPI SCI and nSMI outputs, and ISA Plug-and-Play v1.0a configuration registers with 480 I/O address options. The device integrates BC-Link bus master, 5-channel 10-bit GP-ADC (10.91 µs conversion, 0–3.3 V range), and 56 GPIO pins with maskable wake-event capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19.2–33 MHz - Enables full-speed communication with host CPU without clock stretching or throttling. |
| Embedded Memory | 64 KB SRAM + 1 KB Boot ROM - Provides executable code space and firmware bootstrap without external memory dependency. |
| Power Planes | VCC0 (battery-backed) + VCC1 (main supply) - Supports RTC-like register retention and fast resume from deep sleep states. |
| Fan Control Accuracy | ±3% from 500–16,000 RPM - Ensures precise thermal regulation across full operational speed range using TACH/PWM feedback loop. |
| I²C/SMBus Controllers | 3 × 8584-style - Each supports master/slave mode and operates on standby power for always-on sensor monitoring. |
| ADC Resolution & Speed | 10-bit, 10.91 µs/channel - Delivers high-fidelity voltage monitoring (e.g., battery, VRM rails) with sub-26 mV resolution. |
| PS/2 Ports | 4 independent - Allows concurrent keyboard, mouse, touchpad, and auxiliary HID device support with 5V-tolerant buffers. |
Pinout & Package
MEC1310-NU-TR is housed in a RoHS-compliant 128-pin VTQFP (14×14×1.0 mm) package with exposed thermal pad. Pin functions include multiplexed LPC signals (LAD[3:0], LFRAME#, LRESET#), PS/2 data/clock pairs, I²C/SMBus channel pins (AB1A/AB1B/AB2A/AB2B/AB3), PECI_DAT/PECI_VREF, FAN_TACH[1:2], PWM[0:4], and 56 GPIOs with configurable drive strength.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Address/Data Bus | Time-multiplexed 4-bit bidirectional bus for configuration and data transfer with host CPU. |
| LFRAME# | LPC Frame Signal | Indicates start/end of LPC transaction cycle; synchronized to PCI_CLK or internal oscillator. |
| nEC_SCI | ACPI SCI Output | Active-low interrupt signal to host southbridge indicating system event (e.g., lid open, thermal trip). |
| FAN_TACH1 | Fan Tachometer Input | Counts pulses from fan tachometer wire to calculate RPM; supports automatic aging/failure detection. |
| PWM0 | Pulse-Width Modulator Output | Drives fan motor speed with 6-bit duty cycle granularity; operational in both active and standby modes. |
| AB1A_DATA | I²C/SMBus Controller 1 Data | Open-drain bidirectional line for SMBus communication with battery, EC, or thermal sensors. |
Key Features
| Feature | Design Value |
|---|---|
| RPM-based Fan Control Algorithm | Uses one TACH input and one PWM output to maintain target RPM with spin-up routine, ramp rate control, and invalid-drive detection. |
| Debug UART (16550A-compatible) | 16-byte FIFO, relocatable to 480 I/O addresses, 15 IRQ options - Enables firmware debug without dedicated debug header. |
| 32.768 kHz Ring Oscillator | 2% frequency accuracy, single-ended input, RSMRST#-gated distribution - Provides fail-safe clock for RTC and wake logic during VCC1 loss. |
| Host/8051 SPI Memory Interface | 3-pin full-duplex, hardware-switched or parallel-shared flash support - Simplifies firmware update and dual-image boot implementation. |
| BC-Link Bus Master Controller | Combined high-speed/low-speed bus master - Enables direct communication with companion chips (e.g., audio codec, PMIC) without CPU intervention. |
Applications
| Ultra-Thin Notebook Power Management | Windows-Based Laptop Keyboard & LED Control |
|---|---|
Use Scenario: Managing system power states (S0–S5), thermal throttling, and battery-backed real-time clock functions in sub-15mm clamshell designs. IC Role / Device Role / Timing Role: ACPI Embedded Controller coordinating SCI events, SMI generation, and VCC0/VCC1 rail sequencing. Use Value: Enables <100 µA standby current and instant resume via VCC0-retained registers and fail-safe ring oscillator timing. |
Use Scenario: Driving 18×8 keyboard matrix, PS/2 mouse/touchpad interfaces, and status LEDs (nBAT_LED, nPWR_LED) in OEM laptop platforms. IC Role / Device Role / Timing Role: 8051-based keyboard controller with 8042-style host interface and programmable scan timing. Use Value: Eliminates need for discrete keyboard controller and reduces BOM count while supporting Windows 10/11 HID compliance. |
| Thermal Monitoring & Fan Control System | System-Level Hardware Monitoring Hub |
Use Scenario: Closed-loop fan speed regulation based on ADC-measured CPU/GPU temperatures and ambient sensor inputs. IC Role / Device Role / Timing Role: Integrated RPM-PWM block with tachometer feedback, aging detection, and ramp-rate control. Use Value: Achieves ±3% RPM accuracy across 500–16k RPM range without external op-amps or microcontrollers. |
Use Scenario: Centralized monitoring of 5 analog channels (e.g., VRM output, battery voltage, thermistor), SMBus peripherals, and PECI 2.0 CPU telemetry. IC Role / Device Role / Timing Role: Multi-protocol sensor hub with GP-ADC, three I²C/SMBus controllers, and PECI interface. Use Value: Reduces host CPU polling load and enables autonomous thermal/fault response via 64 maskable wake events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar embedded controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IT8512E | LPC interface, 8051 core, 64KB SRAM, but lacks PECI 2.0 and BC-Link; uses QFP-128 but different pinout. | No native PECI support limits CPU telemetry integration; no BC-Link restricts companion chip interconnect. | Select when PECI and BC-Link are not required and legacy BIOS compatibility is prioritized. |
| W83793G | Super I/O with LPC interface, 128KB Flash, but no embedded 8051 core; relies on host CPU for firmware execution. | Requires host-side driver stack for fan/thermal control; no autonomous wake-event processing or VCC0 retention. | Select for cost-sensitive desktop motherboards where host CPU handles all EC logic. |
Compared with IT8512E and W83793G, the MEC1310-NU-TR delivers autonomous power management via its integrated 8051 core, VCC0-backed registers, and PECI 2.0-enabling true "instant-on" behavior and reduced host CPU overhead in modern notebook platforms.
Availability
MEC1310-NU-TR is available at Aetrix Electronics and suitable for ultra-thin notebook design, Windows OEM platform development, and industrial embedded systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MEC1310-NU-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and embedded control solutions, with ISO/TS-16949 certified manufacturing and global technical support.
The MEC1310-NU-TR belongs to Microchip's Embedded Controller product line, designed specifically for ACPI-compliant notebook I/O subsystems requiring integrated keyboard control, thermal management, and low-power system orchestration.
FAQ
What is the operating voltage range for the MEC1310-NU-TR?
The MEC1310-NU-TR operates at 3.3 V nominal (VCC1), with 5 V–tolerant buffers on all PS/2 pins. It features two independent power domains: VCC0 (battery-backed, typically 3 V) for retaining 64 bytes of registers and status, and VCC1 (3.3 V main supply) for core logic and peripherals. This dual-rail architecture enables reliable operation during battery-only conditions and seamless transition between AC and DC power sources in notebook systems.
Does the MEC1310-NU-TR support PECI 2.0 for CPU thermal telemetry?
Yes, the MEC1310-NU-TR includes native PECI 2.0 interface (PECI_DAT and PECI_VREF pins) compliant with Intel Platform Environment Control Interface specification. It enables direct readout of CPU die temperature, thermal throttle status, and power metrics without host CPU intervention-critical for dynamic fan control and thermal policy enforcement in modern Windows notebooks.
How many I²C/SMBus controllers does the MEC1310-NU-TR integrate, and what are their capabilities?
The MEC1310-NU-TR integrates three 8584-style I²C/SMBus controllers. Two controllers each have two dedicated pin sets (AB1A/AB1B and AB2A/AB2B), while the third uses a single set (AB3). All operate on standby power, support master/slave mode under 8051 control, and enable concurrent communication with battery gas gauges, thermal sensors, and smart chargers-even when the main system is in S3/S5 sleep states.
What is the function of the BC-Link interface in the MEC1310-NU-TR?
The BC-Link interface in the MEC1310-NU-TR is a combined high-speed/low-speed bus master controller that enables direct, CPU-bypass communication with companion chips such as audio codecs, PMICs, or security modules. It supports both burst-mode transfers for audio streaming and packet-based messaging for control commands-reducing latency and host CPU load in complex notebook I/O architectures.
Can the MEC1310-NU-TR execute firmware directly from internal memory?
Yes, the MEC1310-NU-TR contains 64 KB of internal executable SRAM preloaded at VCC1 power-up via the HOST/8051 SPI Memory Interface. This SRAM serves as primary program space for the embedded 8051 core, eliminating external code memory requirements. A separate 1 KB boot ROM provides initial startup routines, and 32 KB of the SRAM is shared with 8051 data space for flexible memory mapping.
MEC1310-NU-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-TQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- I/O Controller
- Core Processor:
- 8051
- Program Memory Type:
- -
- Controller Series:
- -
- RAM Size:
- 64K x 8
- Interface:
- ACPI, BC-Link, I2C/SMBus, LPC, PECI, PS/2, SPI
- Number of I/O:
- 56
- Voltage - Supply:
- 3.3V
- Operating Temperature:
- 0°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 128-VTQFP (14x14)
MEC1310-NU-TR FAQ
1.How can I place an order for MEC1310-NU-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for MEC1310-NU-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MEC1310-NU-TR reliable?
The price and inventory of MEC1310-NU-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MEC1310-NU-TR is usually 5 days.
3.What payment methods are accepted for MEC1310-NU-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MEC1310-NU-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MEC1310-NU-TR?
MEC1310-NU-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MEC1310-NU-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MEC1310-NU-TR?
For technical support, including MEC1310-NU-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MEC1310-NU-TR requirements.
6.How does Aetrix verify that MEC1310-NU-TR is sourced from the original manufacturer or authorized distributors?
All MEC1310-NU-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MEC1310-NU-TR meets industry standards.
7.What is the process for return or replacement of MEC1310-NU-TR?
All MEC1310-NU-TR units undergo pre-shipment inspection (PSI). If there is an issue with MEC1310-NU-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MEC1310-NU-TR part is unused and in its original packaging.
Return procedure for MEC1310-NU-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MEC1310-NU-TR Tags

-
CYPD3175-24LQXQ
Infineon Technologies

-
SLB9672VU20FW1523XTMA1
Infineon Technologies

-
SLB9670VQ20FW785XTMA1
Infineon Technologies

-
SLB9672XU20FW1523XTMA1
Infineon Technologies

-
SLB9673XU20FW2613XTMA1
Infineon Technologies

-
CYPD3125-40LQXIT
Infineon Technologies

-
AT97SC3204-U2A1A-20
Microchip Technology

-
AT97SC3204-U2A1A-10
Microchip Technology

-
SLM9670AQ20FW1311XTMA1
Infineon Technologies

-
SLB9672XU20FW1613XTMA1
Infineon Technologies

-
SLB9672AU20FW1613XTMA1
Infineon Technologies

-
SLB9673AU20FW2613XTMA1
Infineon Technologies
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

