Monolithic Power Systems Inc. MP1906DS-LF-P

Overview

MP1906DS-LF-P from Monolithic Power Systems is an 80V half-bridge gate driver IC designed to control two external N-channel MOSFETs in high-efficiency DC-DC converters. It features independent HPWM/LPWM inputs, 150ns internal dead time, 80ns propagation delay, and under-voltage lockout on both VCC and bootstrap rails-enabling reliable operation in telecom power supplies up to 80V input.

For engineers reviewing the MP1906DS-LF-P datasheet, MP1906DS-LF-P pinout, MP1906DS-LF-P application, or MP1906DS-LF-P equivalent, key selection criteria include bootstrap-supplied high-side drive capability, shoot-through prevention logic, thermal performance in SOIC8, and compatibility with 3.3V/5V PWM controllers in high-frequency half-bridge topologies.

Technical Context

The MP1906 integrates level-shifted high-side drive with a floating bootstrap supply (BT–SW), enabling operation with VSW up to +80V. Its dual-input architecture accepts asynchronous HPWM and LPWM signals while enforcing hardware-based input-signal-overlap protection and fixed 150–250ns dead time between TG and BG transitions.

UVLO circuitry independently monitors VCC (8.2–9.4V threshold) and VBT (4.5–6.5V threshold), forcing both outputs low during undervoltage conditions. The device delivers ±1A peak sink/source current per channel with <0.7V low-side and <1.7V high-side output voltage drop at 100mA load.

Key Specifications

Pinout & Package

MP1906DS-LF-P uses an 8-pin SOIC package (JEDEC MS-012, variation AA) with exposed pad not present; thermal dissipation relies on PCB copper area and θ_JA = 90°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with IR2104S and LM5109BMAX, MP1906DS-LF-P uniquely combines 80V switch-node tolerance, independent dual-rail UVLO, and sub-100ns propagation delay-making it optimal for high-reliability, high-input-voltage half-bridge designs where timing integrity and fault robustness are critical.

Availability

MP1906DS-LF-P is available at Aetrix Electronics and suitable for telecom DC-DC converters, avionics power supplies, and active-clamp forward converters requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for MP1906DS-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan.

The MP1906 belongs to MPS's high-voltage gate driver product line, engineered specifically for robust half-bridge control in demanding power conversion applications including telecom infrastructure, industrial motor drives, and aerospace-grade DC-DC modules.

FAQ

What bootstrap capacitor value is recommended for MP1906DS-LF-P?

A 1µF X7R ceramic capacitor is specified in the datasheet for BT-to-SW placement. This value ensures sufficient charge storage to sustain high-side drive during maximum duty cycle operation while maintaining low ESR for fast recharge. Larger values (e.g., 2.2µF) may improve margin under heavy load but increase board area and cost without measurable benefit in typical 50–100kHz applications.

Does MP1906DS-LF-P support 100% duty cycle on the high-side MOSFET?

No. Due to its bootstrap architecture, MP1906DS-LF-P cannot maintain high-side conduction indefinitely-the bootstrap capacitor discharges over time without periodic SW node oscillation. Continuous high-side operation requires external high-side supply or a charge-pump driver; this part is intended for PWM-driven half-bridge topologies with alternating switching.

How does the input-signal-overlap protection function without external logic?

The MP1906 contains internal combinational logic that detects simultaneous high states on HPWM and LPWM. When both inputs are high, the driver forces both TG and BG outputs low-regardless of prior state-preventing shoot-through. This is implemented in silicon and requires no configuration or external components.

Can MP1906DS-LF-P drive GaN FETs?

Yes, with design attention. Its 1A peak sink/source and 80ns propagation delay meet basic GaN gate drive requirements, but designers must verify gate loop inductance, add RC snubbers if needed, and ensure bootstrap capacitor ESR is low enough to support fast recharge at high frequencies (>300kHz). The 50V/ns dV/dt limit on SW must also be respected.

What is the minimum input pulse width supported by MP1906DS-LF-P?

The datasheet specifies a minimum input pulse width of 50ns for reliable output toggling. This allows operation up to ~300kHz PWM frequency with practical dead time and rise/fall margins. Pulses shorter than 50ns may not register due to internal signal filtering and propagation delays through the protection logic.

Is there a recommended PCB layout practice for minimizing noise coupling on HPWM/LPWM inputs?

Route HPWM and LPWM as matched-length, tightly coupled differential-like traces away from SW and power loops; place 100Ω series resistors near the IC pins; use ground guard traces on both sides; and avoid routing over split planes. These practices reduce susceptibility to dv/dt-induced glitches that could trigger unintended switching.

Does MP1906DS-LF-P include thermal shutdown protection?

Yes. Internal thermal shutdown activates at TJ ≥ 150°C, forcing both TG and BG outputs low until junction temperature falls below the hysteresis threshold (~140°C). This protects against sustained overload or inadequate heatsinking but is not intended as a substitute for proper thermal design per the 90°C/W θ_JA specification.