Monolithic Power Systems Inc. MP5470GL-0000-P

Overview

MP5470GL-0000-P from Monolithic Power Systems is a digital power management IC integrating four synchronous buck converters (3A/3A/2A/2A) with I²C and multi-time programmable (MTP) configuration, operating from 4V–16V input, delivering adjustable outputs (0.78V/0.78V/1.8V/3.3V), and featuring COT control for fast transient response-used in FPGA-based systems requiring tightly sequenced, low-noise rail generation.

For engineers reviewing the MP5470GL-0000-P datasheet, MP5470GL-0000-P pinout, MP5470GL-0000-P application, or MP5470GL-0000-P equivalent, key selection criteria include per-channel current capability, MTP-configurable power sequencing, out-of-phase switching to reduce input ripple, GPIO reconfigurability (PG/ADD/SYNC/Port), and thermal shutdown behavior at 160°C with 20°C hysteresis.

Technical Context

The MP5470 implements constant-on-time (COT) control across all four buck channels, enabling sub-100µs load transient recovery without external compensation. Each channel supports independent soft-start timing (3.1–6.6ms), valley-current OCP (4.2A/4.2A/3A/3A), and out-of-phase operation (0°/90°/180°/270°) to minimize input capacitor RMS current.

Its dual-input architecture (VIN1 powers Buck1/Buck4/VCC; VIN2 powers Buck2/Buck3) enables flexible PCB layout and redundancy, while the integrated 3.3V VCC LDO supplies internal logic and drivers. The I²C slave interface (address 0x68 default) and MTP e-Fuse allow persistent register storage for voltage, sequence, mode (PFM/PWM), and phase settings-even after power loss.

Key Specifications

Pinout & Package

MP5470GL-0000-P is housed in a thermally enhanced QFN-22 (3mm × 4mm) package with exposed thermal pad, optimized for high-power density and low θJA (29°C/W on 4-layer board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail digital PMIC applications.

Compared with TPS650860A0RSMT and ISL95852IRZ, MP5470GL-0000-P uniquely combines MTP persistence, GPIO multi-functionality, and out-of-phase switching-enabling standalone, field-updatable, low-EMI power sequencing without host intervention.

Availability

MP5470GL-0000-P is available at Aetrix Electronics and suitable for enterprise SSD, NVDIMM, DSLR, and FPGA-based designs requiring stable component supply, long-term lifecycle support, and consistent MTP configuration across production batches.

Supply support for MP5470GL-0000-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management solutions, with over two decades of expertise in DC/DC conversion, motor drivers, and battery management.

The MP5470 belongs to MPS's digital PMIC product line, designed specifically for space-constrained, high-reliability applications demanding programmable sequencing, real-time telemetry, and robust fault protection-targeting datacenter, imaging, and programmable logic markets.

FAQ

What is the default I²C slave address for MP5470GL-0000-P?

The default I²C slave address is 0x68. This can be changed to one of four alternatives (0x69, 0x6A, 0x6B) by configuring the GPIO pin as ADD and applying specific voltage thresholds (20%, 33%, 56%, or 80% of VCC) during power-up-enabling multiple MP5470 devices on the same bus without address conflict.

How does the MP5470 handle pre-biased outputs during startup?

The MP5470 supports monotonic pre-bias start-up: if an output is already charged, the internal bootstrap capacitor refreshes, and the soft-start reference ramps only after the sensed FB voltage falls below the rising reference. This prevents reverse current flow and ensures controlled ramp-up even into partially powered systems.

Can the MP5470 operate with separate VIN1 and VIN2 supplies?

Yes-VIN1 powers Buck1/Buck4/VCC, and VIN2 powers Buck2/Buck3. They may be supplied from independent sources (e.g., 5V and 12V rails), but must both remain within 4V–16V. For most applications, connecting VIN1 and VIN2 together simplifies design and ensures consistent UVLO behavior across all channels.

What protection features are implemented per buck channel?

Each buck channel includes valley-current OCP (programmable via MTP), output OVP (120% VREF with discharge mode), soft-start limiting, and thermal foldback. Global protections include input UVLO (5.8V), VCC UVLO (3.0V), and junction thermal shutdown (160°C). All protections are latched or hiccup-mode depending on fault type.

Is the MP5470GL-0000-P RoHS and halogen-free compliant?

Yes-MP5470GL-0000-P is lead-free, halogen-free, and fully compliant with the EU RoHS directive. It meets MPS's green policy standards, with material declarations available on the Monolithic Power Systems website under Quality Assurance documentation.

How is power-good signaling implemented across multiple rails?

Each buck has an internal PG bit (D4–D7 in status register) that asserts when its FB voltage exceeds 92% VREF after a configurable delay (default 200µs). The GPIO pin can be configured as a wired-AND open-drain PG output-pulled low if any enabled rail drops below 87% VREF or during UVLO/OTP events.

What is the minimum off-time specification for Buck1 and Buck2?

The minimum off-time for Buck1 and Buck2 is 113ns (typical), enabling stable operation at high duty cycles (e.g., 0.78V output from 5V input) without pulse-skipping artifacts. This parameter is guaranteed by engineering characterization and supports reliable CCM operation down to ~10% duty cycle.