Monolithic Power Systems Inc. MP5470GL-0000-Z

Overview

MP5470GL-0000-Z from Monolithic Power Systems is a digital quad-buck power management IC integrating four synchronous DC/DC converters (3A/3A/2A/2A) with I²C and multi-time programmable (MTP) configuration, operating from 4V–16V input, delivering preset or dynamically adjustable outputs (0.78V/0.78V/1.8V/3.3V), and supporting out-of-phase switching for reduced input ripple in enterprise SSD and FPGA-based power systems.

For engineers reviewing the MP5470GL-0000-Z datasheet, MP5470GL-0000-Z pinout, MP5470GL-0000-Z application, or MP5470GL-0000-Z equivalent, this page delivers verified technical context, validated pin functions, confirmed MTP/I²C configurability, real-world soft-start timing (3.1–6.6 ms), and precise thermal shutdown behavior (160°C trip, 20°C hysteresis).

Technical Context

The MP5470 employs constant-on-time (COT) control across all four buck channels to ensure fast load transient response (<100 µs recovery), with independent valley-current limiting (4.2A/4.2A/3A/3A) and programmable switching frequency up to 1.6 MHz. Each channel supports pre-biased start-up and monotonic soft-start with individually configurable delay and ramp time.

Its dual-input architecture (VIN1 powers Buck1/Buck4/VCC; VIN2 powers Buck2/Buck3) enables flexible PCB layout and remote sensing via dedicated SGND1/SGND2 pins. The integrated 3.3V VCC LDO, GPIO-configurable ADD/PG/SYNC output, and I²C slave interface (3.4 MHz max) support system-level sequencing, fault monitoring, and dynamic voltage scaling in space-constrained 12V systems.

Key Specifications

Pinout & Package

MP5470GL-0000-Z is housed in a thermally enhanced QFN-22 package (3 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is marked by a dot; top-side marking includes "MP" prefix, year/week code, "5470", and lot number.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-buck PMIC applications.

Compared with RTQ2132B-QA and ISL91211BIKZ-T7A, MP5470GL-0000-Z uniquely combines MTP nonvolatile configuration storage, integrated bootstrap capacitors, and out-of-phase switching in a 3×4 mm QFN-reducing design iteration cycles and PCB footprint while enabling field-programmable power policies.

Availability

MP5470GL-0000-Z is available at Aetrix Electronics and suitable for enterprise SSD, NVDIMM, DSLR camera, and FPGA-based industrial controller designs requiring stable component supply, long-term lifecycle assurance, and production-ready qualification.

Supply support for MP5470GL-0000-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management solutions, with over two decades of expertise in DC/DC conversion, battery management, and motor drivers.

The MP5470 belongs to MPS's digital PMIC product line, engineered specifically for high-density computing and storage platforms where programmable sequencing, compact size, and robust transient performance are critical.

FAQ

What is the default I²C slave address for MP5470GL-0000-Z?

The default I²C slave address is 0x68. This value is stored in the MTP and can be modified using the GPIO ADD function, which supports four distinct addresses (0x68, 0x69, 0x6A, 0x6B) based on applied voltage thresholds (20%, 33%, 56%, 80% of VCC) on the GPIO pin during power-up.

Can MP5470GL-0000-Z operate with separate 12V and 5V input rails?

No - VIN1 and VIN2 must be connected together per the datasheet recommendation. VIN1 powers Buck1/Buck4/VCC; VIN2 powers Buck2/Buck3. Separating them violates internal biasing and may cause undefined behavior or failure to regulate. Both inputs share the same 4V–16V range and require common decoupling.

How does the MP5470 handle pre-biased outputs during startup?

The MP5470 supports monotonic pre-bias start-up: if an output is already charged, the internal BST capacitor refreshes, and the soft-start reference ramps only after sensed FB voltage falls below the rising reference. This prevents reverse current flow and ensures controlled, non-monotonic-free ramping into existing voltage rails.

Is the GPIO pin capable of driving an external load in Output Port mode?

Yes - when configured as Output Port via MTP/I²C, GPIO operates as an open-drain output with programmable logic state (high/low). It can sink ≥1 mA at 0.4 V (per datasheet), making it suitable for driving LEDs, enabling secondary regulators, or signaling status to microcontrollers without additional buffering.

What protection features are active during shutdown mode?

In shutdown (EN/SYNCI < 1.21 V), UVLO, thermal warning, and OVP remain active. Shutdown current is 70–140 µA. I²C communication and MTP access stay functional, allowing register reads and configuration updates even while power stages are disabled - enabling diagnostics and preparation for next power cycle.

Does MP5470GL-0000-Z support external synchronization of all four buck channels?

Only Buck1's switching edge synchronizes directly to the external clock applied to EN/SYNCI. Buck2–Buck4 maintain their programmed 90° phase offsets relative to Buck1. This preserves out-of-phase operation while aligning the entire quad-buck system to an external timing source for EMI reduction or system-level clock domain coordination.