Monolithic Power Systems Inc. MP5520GQJ-0000-P

Overview

MP5520GQJ-0000-P from Monolithic Power Systems is a power-loss protection PMIC for enterprise SSDs, integrating dual e-fuses (2.7–16V and 2.7–6V inputs), a 36V bidirectional buck-boost converter for capacitor-based backup, and a bidirectional power-sharing converter. It delivers up to 10A peak backup current, supports I²C configuration, and operates in QFN-37 (5mm×6mm) with CSTRG health monitoring.

For engineers reviewing the MP5520GQJ-0000-P datasheet, MP5520GQJ-0000-P pinout, MP5520GQJ-0000-P application, or MP5520GQJ-0000-P equivalent, key selection criteria include dual-input e-fuse R_DS(ON) (20/22 mΩ), configurable VSTRG up to 36V, bidirectional power-sharing mode selection (buck/boost), I²C-controlled brownout thresholds, and integrated 8-bit ADC monitoring VINx/IINx/PINx at 60 kSPS.

Technical Context

The MP5520 implements three tightly coordinated subsystems: dual independent e-fuses with reverse-current blocking and soft-start control; a constant-on-time (COT)-controlled 36V bidirectional PLP converter that charges high-voltage storage capacitors and releases energy during VIN loss with <5% voltage drop in transition; and a separately configurable bidirectional power-sharing converter supporting boost-sharing (e.g., 5V→12V) or buck-sharing (e.g., 12V→5V) between input rails.

System-level intelligence includes MTP-programmable registers (up to 1,000 writes), real-time CSTRG health diagnostics, dual interrupt outputs (INT1 for OC/OV/CSTRG fault; INT2 for CAPTEST_DONE), and four PFI trigger modes based on DET1/DET2 logic combinations - enabling precise coordination of power fail response across multi-rail SSD architectures.

Key Specifications

Pinout & Package

MP5520GQJ-0000-P is housed in a thermally enhanced QFN-37 package (5mm × 6mm, 0.5mm pitch) with exposed thermal pad. Dual ground pins (GND1, GND2) and wide copper routing are required for high-current paths (e.g., SW1/SW2, VB1/VB2).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-loss protection applications.

Compared with TPS25750 and LTC4421, MP5520GQJ-0000-P uniquely integrates dual e-fuses, bidirectional power-sharing, and 36V PLP in one QFN-37 package - reducing solution size by 60%, eliminating 12+ passives, and enabling field-updatable protection profiles via MTP.

Availability

MP5520GQJ-0000-P is available at Aetrix Electronics and suitable for enterprise SSDs, datacenter NVMe modules, PCIe accelerator cards, and SAS storage backplanes requiring stable component supply, long-term lifecycle support, and qualified automotive-grade reliability.

Supply support for MP5520GQJ-0000-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs for computing, cloud infrastructure, and industrial applications, with design centers in the US, China, and Taiwan.

The MP5520 belongs to MPS's Power Loss Protection (PLP) product line, engineered specifically for high-density, high-reliability SSDs requiring seamless transition between main power and capacitor-based backup without firmware intervention.

FAQ

What is the maximum storage capacitor (CSTRG) voltage rating supported by MP5520GQJ-0000-P?

The MP5520GQJ-0000-P supports up to 36V on the STRG pin, with absolute maximum rating of 40V. The recommended operating range is 3V to 36V. External CSTRG must be rated for ≥36V DC with sufficient ripple current capability; typical values are 470µF to 2200µF tantalum or polymer capacitors.

How does the MP5520 handle simultaneous input failures on VIN1 and VIN2?

In SAS mode (EN2 = high), the MP5520 requires both VIN1 and VIN2 to exceed their respective UVLO thresholds before enabling e-fuses. If both fail simultaneously, DET1 and DET2 trigger together, causing PFI to assert high and initiating immediate buck-release from CSTRG to sustain VB1/VB2 - with no delay beyond the configured tDVDT soft-start window.

Can the power-sharing converter operate without the PLP function enabled?

Yes. The power-sharing converter operates independently in standalone buck or boost mode regardless of PLP status. When configured in standalone buck mode (via FB1 feedback and I²C register), it regulates VB1 or VB2 using external resistors - enabling continuous cross-rail voltage conversion even when CSTRG is uncharged or disconnected.

What is the purpose of the RT pin, and how is it used in CSTRG health testing?

The RT pin connects an external resistor to set the discharge current during capacitor health tests. The MP5520 applies a controlled discharge pulse through RT, measures voltage decay slope, and calculates ESR and capacitance - reporting results via I²C registers (40h–43h). This enables predictive maintenance without external test equipment.

Does MP5520GQJ-0000-P support daisy-chained I²C configurations for multi-PMIC systems?

No. Each MP5520 uses a fixed 3-bit I²C address set by the ADDR pin (33h/35h/37h), with no hardware address offset or software-configurable ID. Multi-PMIC systems require individual ADDR pin strapping or I²C bus multiplexing (e.g., PCA9548A) to avoid address conflicts.

What thermal derating applies above 85°C ambient temperature?

With θJA = 29.5°C/W, the MP5520GQJ-0000-P dissipates ≤4W continuously. At 100°C ambient, maximum allowable power drops to ~2.7W ((150−100)/29.5). Derating is linear; operation above 125°C junction triggers thermal shutdown. Layout with 2oz copper and thermal vias under the exposed pad is mandatory for full-load operation above 70°C ambient.

How is the 10A peak backup current achieved with a single inductor?

The PLP converter uses a single coupled inductor (LPLP) shared between charge and release phases. During charge, energy transfers from VIN to CSTRG via buck topology; during release, the same inductor enables buck operation from CSTRG to VBx. Peak current is limited by internal LS-FET valley current sensing (3.6A typ) and external current-sense resistor scaling.