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Monolithic Power Systems Inc. MP5520GQJ-0000-Z
- Part No.:
- MP5520GQJ-0000-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Category:
- Power Management - Specialized
- Package:
- 37-PowerVFQFN
- Datasheet:
-
MP5520GQJ-0000-Z.pdf
- Description:
- 2.7V TO 16V, POWER LOSS PROTECTI
- Quantity:
- Payment:
- Shipping:
Inventory:2,918
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Product details
Overview
MP5520GQJ-0000-Z from Monolithic Power Systems is a power loss protection (PLP) PMIC for enterprise SSDs, integrating dual e-fuses (20mΩ/22mΩ), a 36V bidirectional buck-boost converter (up to 10A peak backup current), and a bidirectional power-sharing converter. It enables seamless hold-up during VIN outage using high-voltage storage capacitors and supports PCIe/SAS mode selection via EN2 pin.
For engineers reviewing the MP5520GQJ-0000-Z datasheet, MP5520GQJ-0000-Z pinout, MP5520GQJ-0000-Z application, or MP5520GQJ-0000-Z equivalent, key selection criteria include dual-input current-limit switching with reverse-current blocking, configurable VSTRG charging and regulated buck release (VBUS_RLS), CSTRG health monitoring, I²C-configurable thresholds, and QFN-37 package thermal performance (θJA = 29.5°C/W).
Technical Context
The MP5520 implements three tightly coordinated subsystems: two independent e-fuses with programmable UVLO, soft-start, and overcurrent protection; a constant-on-time (COT)-controlled 36V PLP converter that charges CSTRG up to 36V and delivers regulated buck output during VIN loss; and a selectable boost/buck power-sharing converter with internal ADC monitoring of VINx, IINx, and PINx at 60kSPS.
Its architecture enables system-level power continuity: e-fuse reverse-current blocking isolates backup energy, while the PLP's COT control minimizes voltage droop during charge-to-backup transition. The MTP memory stores up to 1,000 configurations, and I²C registers allow real-time adjustment of thresholds, current limits, and operating modes without hardware changes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.7V–16V (E-Fuse 1), 2.7V–5.7V (E-Fuse 2): Enables dual-rail input support for 12V/5V SSD power domains. |
| RDS(ON) | 20mΩ (E-Fuse 1), 22mΩ (E-Fuse 2): Minimizes conduction loss and thermal rise under 2A continuous load. |
| VSTRG Range | 3V–36V: Supports high-energy density storage with minimal capacitor size via patented energy management. |
| Backup Current | Up to 10A peak / 7A valley: Sustains critical SSD write-caching during 10–200ms power interruption. |
| Switching Frequency | Configurable 1MHz (PLP release, power-sharing): Balances efficiency, EMI, and inductor size in compact layouts. |
| ADC Resolution | 8-bit @ 60kSPS: Enables real-time telemetry of input voltages, currents, and power for predictive health monitoring. |
| Package | QFN-37 (5mm × 6mm): Optimized thermal dissipation (θJC = 15.5°C/W) for high-power density SSD modules. |
Pinout & Package
MP5520GQJ-0000-Z is housed in a thermally enhanced QFN-37 (5mm × 6mm) package with exposed thermal pad. Pin numbering follows standard top-view layout per MPS datasheet Rev. 1.0 (Jan 2024). Dual ground pins (GND1, GND2) and dedicated bootstrap (BST1/BST2), sense (FBS/FBR), and configuration (ADDR, EN2, RT) terminals enable precise system integration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 BST1 | Power-sharing HS-FET bootstrap | Drives high-side MOSFET gate; requires 100nF BST1–SW1 capacitor for reliable switching. |
| 8 FBS | Storage voltage feedback | Sets VSTRG via external resistor divider; determines charge termination and energy capacity. |
| 9 FBR | Release voltage feedback | Configures regulated VBUS_RLS during backup; default threshold 0.8V enables 6V/12V bus hold-up. |
| 15 STRG | High-voltage storage node | Connects directly to CSTRG (up to 36V); carries full backup energy path with low-impedance routing. |
| 31 VIN1 / 17 VIN2 | Dual input rails | Independent 16V/6V inputs with separate UVLO, soft-start, and current limiting for fault isolation. |
| 34 VB1 / 16 VB2 | E-fuse outputs | Protected downstream rails; each provides reverse-current blocking and overvoltage clamping (13.7V/6.0V). |
| 23 SCL / 22 SDA | I²C interface | 3.4MHz-capable bus for real-time register access, status polling, and dynamic configuration updates. |
Key Features
| Feature | Design Value |
|---|---|
| Dual e-fuse current limiting | Configurable 1.7–2.3A per channel with 20/22mΩ RDS(ON), enabling precise fault containment in multi-rail SSDs. |
| PLP COT control | Eliminates voltage droop during charge-to-buck transition by maintaining fixed on-time during backup mode. |
| Capacitor health monitoring | RT-pin-based discharge test quantifies CSTRG ESR degradation over time, preventing unexpected hold-up failure. |
| PCIe/SAS mode selection | EN2 pin configures startup sequencing: simultaneous e-fuse turn-on (SAS) or staggered (PCIe) for compliance with spec timing. |
| Programmable power failure response | PFI/INT1/INT2 open-drain outputs deliver prioritized alerts (OV, OC, CSTRG fail) with maskable interrupt sources. |
Applications
| Enterprise SSD Power Backup | Datacenter NVMe Drive Hold-Up |
|---|---|
|
Use Scenario: Maintaining DRAM cache integrity during unexpected AC loss in U.2/U.3 NVMe SSDs. IC Role / Device Role / Timing Role: PLP PMIC acts as system-level power continuity manager-charging CSTRG during normal operation and releasing regulated 12V/5V during <200ms outage. Use Value: Guarantees safe write-caching completion with ≤100μs transition time and no data corruption under JEDEC JESD219 hold-up requirements. |
Use Scenario: Supporting hot-plug resilience in rack-scale datacenter storage systems with redundant PSUs. IC Role / Device Role / Timing Role: Dual e-fuses isolate upstream 12V/5V supplies; power-sharing converter balances load between rails during brownout events. Use Value: Enables seamless rail switchover without host intervention, reducing downtime during PSU maintenance or failure. |
| Industrial RAID Controller Protection | AI Accelerator Module UPS |
|
Use Scenario: Preventing metadata corruption in industrial RAID controllers subjected to unstable 24V DC input. IC Role / Device Role / Timing Role: E-fuse 1 accepts 2.7–16V input; PLP converter regulates 5V VBUS_RLS to sustain FPGA configuration and flash write buffers. Use Value: Delivers 7A valley current for ≥15ms hold-up using 2200μF CSTRG, meeting IEC 61000-4-11 immunity standards. |
Use Scenario: Securing volatile HBM2E memory state during brief power dips in AI training accelerators. IC Role / Device Role / Timing Role: Power-sharing converter operates in buck mode to supply 0.8V–1.2V auxiliary rails; CSTRG health monitoring prevents latent capacitor failure. Use Value: Achieves <1% voltage deviation during 10A transient load steps, preserving accelerator compute fidelity during power transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power loss protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65988DHAR | USB-C PD controller with integrated PLP; lacks dual e-fuses and standalone 36V storage capability. | Targeted at portable systems with USB-C power delivery; not rated for enterprise SSD thermal or hold-up requirements. | Select MP5520GQJ-0000-Z when dual-rail input protection, >10A backup current, and CSTRG health monitoring are mandatory. |
| MAX20804ATG+T | Single-channel 36V PLP IC with 5A peak backup; no power-sharing converter or MTP configuration memory. | Supports basic hold-up only; cannot manage inter-rail power sharing or PCIe/SAS mode sequencing. | Choose MP5520GQJ-0000-Z for systems requiring coordinated dual-e-fuse control, I²C telemetry, and adaptive power-sharing topology. |
Compared with TPS65988DHAR and MAX20804ATG+T, MP5520GQJ-0000-Z uniquely integrates dual e-fuses, bidirectional power sharing, and CSTRG health monitoring in a single QFN-37 package-enabling compact, high-reliability PLP solutions for demanding enterprise SSD and datacenter applications where rail coordination and predictive maintenance are critical.
Availability
MP5520GQJ-0000-Z is available at Aetrix Electronics and suitable for enterprise SSDs, datacenter NVMe drives, industrial RAID controllers, and AI accelerator modules requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for MP5520GQJ-0000-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design expertise in DC/DC converters, motor drivers, and power loss protection solutions.
The MP5520 belongs to MPS's enterprise-grade PLP PMIC product line, engineered specifically for JEDEC-compliant SSD power continuity, emphasizing dual-rail robustness, capacitor health awareness, and PCIe/SAS protocol alignment.
FAQ
What is the maximum storage voltage (VSTRG) supported by MP5520GQJ-0000-Z?
The MP5520GQJ-0000-Z supports up to 36V on the STRG pin, with absolute maximum rating of +40V. Operation above 36V risks violating the recommended operating condition and may trigger internal protection circuits or degrade long-term reliability. The FBS feedback network must be configured to clamp VSTRG at or below 36V during charging.
How does the MP5520 handle reverse current blocking during backup mode?
MP5520GQJ-0000-Z blocks reverse current through both e-fuses using internal MOSFET control logic. When VIN drops, the e-fuse gates are actively held off, preventing energy backflow from VB1/VB2 into VIN1/VIN2. This ensures stored energy in CSTRG is exclusively directed to the load during buck release, maximizing usable hold-up time.
Can the power-sharing converter operate independently of the PLP function?
Yes-the power-sharing converter functions in standalone buck or boost mode regardless of PLP activity. In standalone buck mode, FB1 regulates output voltage (default 0.6V reference); in boost mode, CT1/VB1 interaction enables rail boosting. Its operation is controlled via I²C registers (0Fh) and EN2 pin configuration, decoupled from STRG voltage or PLP state.
What is the role of the RT pin in capacitor health monitoring?
The RT pin connects an external resistor to set the discharge current during CSTRG health tests. By measuring voltage decay rate across known resistance, the MP5520 calculates effective series resistance (ESR) and capacitance drift. Results are reported via I²C register 40h, enabling predictive maintenance before hold-up time falls below specification.
Is the MP5520GQJ-0000-Z pin-compatible with other MP5520 variants?
Yes-all MP5520 variants (e.g., MP5520GQJ-1234-Z) share identical QFN-37 pinout, thermal pad layout, and electrical interface. The "0000" suffix denotes default MTP configuration; reprogramming via I²C or EVKT-MP5520 does not affect mechanical or signal compatibility.
Does the MP5520 support automatic mode switching between PCIe and SAS protocols?
No-mode selection is static and determined by the EN2 pin voltage at power-up. Pulling EN2 high selects SAS mode (simultaneous e-fuse enable); pulling low selects PCIe mode (independent e-fuse control). No runtime switching is supported; reconfiguration requires reset or power cycle.
What is the minimum recommended CSTRG value for 10ms hold-up at 5A load?
Based on typical performance curves (Figure 13, Rev. 1.0), a 1000μF CSTRG supports ≥10ms hold-up at 5A with VSTRG = 27.2V and VBUS_RLS = 6V. For margin, MPS recommends ≥2200μF ceramic or hybrid polymer capacitors rated for 36V to ensure longevity and low ESR across temperature.
MP5520GQJ-0000-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 37-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Solid State Drives (SSD)
- Current - Supply:
- -
- Voltage - Supply:
- 2.7V ~ 5.7V, 16V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 37-QFN (5x6)
MP5520GQJ-0000-Z FAQ
1.How can I place an order for MP5520GQJ-0000-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for MP5520GQJ-0000-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MP5520GQJ-0000-Z reliable?
The price and inventory of MP5520GQJ-0000-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MP5520GQJ-0000-Z is usually 5 days.
3.What payment methods are accepted for MP5520GQJ-0000-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MP5520GQJ-0000-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MP5520GQJ-0000-Z?
MP5520GQJ-0000-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MP5520GQJ-0000-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MP5520GQJ-0000-Z?
For technical support, including MP5520GQJ-0000-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MP5520GQJ-0000-Z requirements.
6.How does Aetrix verify that MP5520GQJ-0000-Z is sourced from the original manufacturer or authorized distributors?
All MP5520GQJ-0000-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MP5520GQJ-0000-Z meets industry standards.
7.What is the process for return or replacement of MP5520GQJ-0000-Z?
All MP5520GQJ-0000-Z units undergo pre-shipment inspection (PSI). If there is an issue with MP5520GQJ-0000-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MP5520GQJ-0000-Z part is unused and in its original packaging.
Return procedure for MP5520GQJ-0000-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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