Monolithic Power Systems Inc. MP8003AGQ-P

Overview

MP8003AGQ-P from Monolithic Power Systems is an IEEE 802.3af/at-compliant powered device (PD) interface controller for Power over Ethernet systems. It integrates a 100V, 0.48Ω hot-swap MOSFET, supports 2-event classification up to Class 4, delivers 120mA inrush and 840mA operational current limiting, and provides auxiliary adapter detection with seamless power switchover-enabling robust PoE-powered security cameras and VoIP phones.

For engineers reviewing the MP8003AGQ-P datasheet, MP8003AGQ-P pinout, MP8003AGQ-P application, or MP8003AGQ-P equivalent, key selection considerations include its QFN-10 package thermal performance, T2P open-drain Type-2 PSE indicator behavior, PG signal timing relative to RTN voltage threshold, and AUX-based wall-adapter priority logic under dual-power scenarios.

Technical Context

The MP8003AGQ-P implements full IEEE 802.3af/at PD interface functionality-including detection (2.7–10.1V signature range), 2-event classification (14.5–20.5V + mark event), and UVLO hysteresis (37.5V turn-on / 31V turn-off). Its internal gate driver controls the integrated 100V pass MOSFET with precise inrush-to-operation transition at RTN = 1.2V after 100ms delay.

It features dual-power arbitration via AUX input: when VDD − VAUX > 2.3V, it disables the hot-swap FET and CLASS function while asserting active-low T2P and high PG-enabling immediate downstream DC/DC enablement from wall adapter without PoE dependency.

Key Specifications

Pinout & Package

The MP8003AGQ-P is housed in a thermally enhanced QFN-10 (3mm × 3mm) package with exposed thermal pad connected to VSS. Pin 9 (NC) must be tied to VSS or left floating per layout guidelines; Pin 2 (FTY) is factory-reserved and requires connection to VSS in application.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE powered device interface applications.

Compared with LT4275AIMSE#PBF and TPS23753APWR, the MP8003AGQ-P uniquely balances 802.3af/at compliance, integrated 100V FET, and seamless AUX switchover in a compact QFN-10 - making it optimal for space-constrained dual-power PoE endpoints without I²C telemetry requirements.

Availability

MP8003AGQ-P is available at Aetrix Electronics and suitable for security camera deployments, VoIP infrastructure upgrades, and WLAN access point manufacturing requiring stable component supply across multi-year production cycles.

Supply support for MP8003AGQ-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with global design centers and AEC-Q100-qualified automotive products.

The MP8003AGQ-P belongs to MPS's PoE Powered Device Interface Controller product line, engineered specifically for IEEE 802.3af/at-compliant endpoints needing integrated hot-swap, classification, and auxiliary power arbitration in minimal footprint.

FAQ

What is the minimum detection resistor value supported for MP8003AGQ-P?

The MP8003AGQ-P requires a 24.9kΩ ±1% resistor between DET and VDD to meet IEEE 802.3af/at signature tolerance (23.7kΩ–26.3kΩ). Lower values risk detection failure due to excessive current draw beyond PSE specification limits.

How does the MP8003AGQ-P handle simultaneous PoE and wall adapter connection?

When both sources are present, the MP8003AGQ-P monitors VDD − VAUX. If this difference exceeds −2.3V, it disables the internal hot-swap MOSFET, turns off CLASS current, asserts T2P low, and pulls PG high - routing power exclusively through the adapter path.

Can the PG signal drive a standard CMOS enable pin directly?

Yes - the internal 7µA pull-up current is sufficient to assert a logic-high signal on typical CMOS EN inputs (e.g., <1µA leakage). For loads requiring >7µA sink current, an external pull-up resistor (e.g., 100kΩ to 3.3V) is recommended to maintain PG high during downstream switching transients.

What is the purpose of the FTY pin, and how should it be connected?

Pin 2 (FTY) is reserved for factory testing and has no user functionality. Per MPS layout guidance, it must be externally connected to VSS in all applications to ensure proper internal biasing and thermal performance.

Does MP8003AGQ-P support IEEE 802.3bt (PoE++)?

No - the MP8003AGQ-P is certified for IEEE 802.3af (15.4W) and 802.3at (30W) only. It lacks the four-pair detection, higher voltage tolerance (>60V), and digital classification required for 802.3bt (60W/90W) operation.

What thermal design practices are critical for reliable MP8003AGQ-P operation?

Mount the exposed thermal pad directly to a solid VSS copper plane with ≥4 thermal vias (0.3mm diameter) to inner layers. Maintain ≥0.5mm clearance between VDD/VSS traces and other nets per IEC60950 creepage requirements, and avoid routing high-speed signals under the QFN body.

How does the 2-event classification sequence work in practice?

The PSE first applies 14.5–20.5V to trigger Class 4 current (40.4mA); then drops to 6.9–10.1V for the mark event (0.5–2mA sink). After repeating this cycle, the PSE confirms Type-2 capability and applies full 48V - at which point MP8003AGQ-P transitions from 120mA inrush to 840mA operation.