Monolithic Power Systems Inc. MP8005DF-LF-P

Overview

MP8005DF-LF-P from Monolithic Power Systems is an IEEE 802.3af-compliant Powered Device (PD) interface and PWM controller in a 20-pin TSSOP-EP package, integrating detection, classification, inrush limiting, thermal protection, and isolated/non-isolated synchronous buck controller functionality. It supports up to 13W PoE power delivery, features a 100V/1Ω integrated main switch, 460mA temperature-compensated current limit, and programmable output voltage via external resistor divider for VoIP phones and security cameras.

For engineers reviewing the MP8005DF-LF-P datasheet, MP8005DF-LF-P pinout, MP8005DF-LF-P application, or MP8005DF-LF-P equivalent, key selection considerations include its dual-gate drive timing control (RDELAY-programmable), VDD UVLO at 38–42V, 220–300kHz switching frequency, and Class 3 classification capability with 4.42kΩ RCLASS.

Technical Context

The MP8005DF-LF-P implements a two-stage PD startup sequence: first, 25kΩ detection and 10.2–13V classification with programmable RCLASS (e.g., 4.42kΩ for Class 3), then controlled inrush current limiting via RILIM (178kΩ typical) to charge input capacitance before enabling the PWM regulator. Its internal logic enforces strict IEEE 802.3af state transitions-detection → classification → power good (PG) assertion-before releasing MAINGATE/SYNCGATE drivers.

It integrates dual gate drivers (16Ω sourcing / 5Ω sinking impedance), error amplifier (0.26–0.46mA/V transconductance), and programmable delay between SYNCGATE falling edge and MAINGATE rising edge (40–200ns via RDELAY resistor). Thermal shutdown activates at 150°C with automatic recovery after VCRST drops below 10.8V.

Key Specifications

Pinout & Package

TSSOP-20 with exposed thermal pad (JEDEC MO-153 compliant); 6.5mm × 4.4mm footprint, 0.65mm pitch, 1.05mm max height. Exposed pad must be soldered to PCB ground plane for thermal performance and EMI reduction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar IEEE 802.3af PD interface applications.

Compared with LT4275IMS#PBF and NCP1094DR2G, the MP8005DF-LF-P uniquely combines full IEEE 802.3af PD functionality with dual-gate synchronous controller and RDELAY-adjustable timing-enabling robust isolated flyback designs without external timing components or secondary controllers.

Availability

MP8005DF-LF-P is available at Aetrix Electronics and suitable for VoIP telephony, security camera systems, and industrial network interface cards requiring stable component supply, RoHS-compliant packaging, and full IEEE 802.3af interoperability.

Supply support for MP8005DF-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, motion control, and automotive applications.

The MP8005 belongs to MPS's IEEE-compliant PoE PD controller product line, designed specifically to simplify implementation of standards-based powered devices in voice, video, and data infrastructure equipment.

FAQ

What is the maximum input voltage rating for MP8005DF-LF-P?

The MP8005DF-LF-P has an absolute maximum VDD rating of +100V, with recommended operating range up to +57V per IEEE 802.3af. Its integrated 100V/1Ω main switch and thermal foldback protect against sustained overvoltage events beyond nominal PSE output.

How does the RDELAY pin affect gate timing in synchronous topologies?

RDELAY sets a programmable delay (40–200ns) between SYNCGATE falling edge and MAINGATE rising edge using an external resistor to AGND. This prevents cross-conduction in synchronous rectifier circuits, directly improving efficiency and preventing MOSFET failure due to shoot-through current.

Can MP8005DF-LF-P support isolated and non-isolated DC-DC topologies?

Yes - it supports both. The COMP/VFB pins provide full error amplifier interface for isolated flyback/forward controllers, while MAINGATE/SYNCGATE drivers enable non-isolated synchronous buck designs. Its architecture explicitly accommodates transformer-coupled feedback loops with adjustable RDELAY timing.

What classification resistor value is required for Class 3 operation?

A 4.42kΩ resistor between CLASS and VSS configures the MP8005DF-LF-P for IEEE 802.3af Class 3 operation, drawing 38–41.2mA during classification to signal a 12.95W power requirement to the PSE. This value is confirmed in the Electrical Characteristics table on page 4 of the datasheet.

Does MP8005DF-LF-P include built-in inrush current limiting?

Yes - it implements active inrush limiting via programmable RILIM (178kΩ typical). During startup, it delivers controlled current to charge the input capacitor until VRTN reaches ~90% of VDD, preventing thermal stress and die heating that would occur with uncontrolled charging.

What is the purpose of the PG (Power Good) output pin?

PG is an active-low, deglitched open-drain output that asserts after VDD/RTN stabilize and internal regulators reach valid operating conditions. Its 75–225μs deglitch prevents false triggering during transient startup, ensuring downstream DC-DC controllers enable only after stable input conditions are confirmed.

Is MP8005DF-LF-P lead-free and RoHS compliant?

Yes - the "-LF" suffix denotes lead-free, RoHS-compliant packaging. All MPS parts adhere to the RoHS directive, and the MP8005DF-LF-P uses matte tin plating on leads and meets JEDEC J-STD-020 moisture sensitivity level 3 requirements.