Monolithic Power Systems Inc. MP8005DF-LF-Z

Overview

MP8005DF-LF-Z from Monolithic Power Systems is an IEEE 802.3af-compliant Powered Device (PD) interface and PWM controller in a 20-pin TSSOP-EP package, integrating detection, classification, inrush limiting, thermal protection, and isolated/non-isolated synchronous buck controller functionality. It supports up to 13W PoE power delivery with 100V/1Ω integrated main switch, 460mA temperature-compensated current limit, and programmable output voltage via external resistor divider. Used in VoIP telephones and security camera systems requiring robust, standards-compliant PoE power conversion.

For engineers reviewing the MP8005DF-LF-Z datasheet, MP8005DF-LF-Z pinout, MP8005DF-LF-Z application, or MP8005DF-LF-Z equivalent, this page delivers verified technical context, validated pin functions, confirmed IEEE 802.3af compliance parameters, real-world application constraints, and traceable alternative selection guidance - all grounded in Monolithic Power's Rev. 1.0 datasheet and official package documentation.

Technical Context

The MP8005DF-LF-Z implements dual-stage PoE startup: first, a 25kΩ detection signature (VDET_ON = 1.9V, VDET_OFF = 11V) followed by classification across 10–21V using RCLASS to define power class (e.g., 4.42kΩ = Class 3). It integrates a 100V-rated main gate driver (16Ω sourcing, 5Ω sinking) and synchronous gate driver with adjustable RDELAY-controlled dead-time (40–200ns).

Its control architecture includes a 220–300kHz PWM oscillator, error amplifier (0.26–0.46mA/V transconductance), soft-start (4μA CSS current), and thermal shutdown at 150°C with automatic recovery after VCRST drops below 10.8V. The device enforces inrush current limiting (120–180mA) and provides active-low PG signaling with 75–225μs deglitch delay.

Key Specifications

Pinout & Package

TSSOP-20-EP (exposed pad) package with 0.65mm pitch, 6.5mm × 4.4mm body, and thermal pad for enhanced power dissipation. Pin 1 marked with dot; pins 10 and 11 are NC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar IEEE 802.3af PD interface applications.

Compared with LT4275AIMSE#PBF and NCP1092DR2G, the MP8005DF-LF-Z uniquely combines full 13W PoE compliance, integrated synchronous PWM control, and RDELAY-tunable dead-time-making it optimal for compact, isolated, high-efficiency PoE-powered devices requiring minimal external components.

Availability

MP8005DF-LF-Z is available at Aetrix Electronics and suitable for VoIP telephony, security camera systems, industrial network cards, and safety-critical backup power applications requiring stable component supply, full IEEE 802.3af compliance, and thermal robustness across –40°C to +85°C ambient.

Supply support for MP8005DF-LF-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power management ICs, with design centers in the US, China, and Taiwan.

The MP8005 belongs to MPS's PoE Powered Device Interface product line, engineered specifically for IEEE 802.3af-compliant endpoints requiring integrated detection, classification, inrush control, and DC-DC regulation in space-constrained networking equipment.

FAQ

What is the maximum continuous power delivery capability of the MP8005DF-LF-Z?

The MP8005DF-LF-Z supports up to 13W of continuous power delivery per IEEE 802.3af Class 3 specifications. Its 100V-rated main switch and 460mA current limit enable reliable operation at 57V input, delivering regulated output power to downstream converters while maintaining thermal shutdown protection at 150°C junction temperature.

How does the RDELAY pin function, and what resistor value achieves 100ns delay?

The RDELAY pin sets dead-time between SYNCGATE falling edge and MAINGATE rising edge to prevent MOSFET cross-conduction. A 100kΩ resistor from RDELAY to AGND yields ~100ns delay, per datasheet Figure 10. Values from 0–200kΩ produce 40–200ns delays; smaller resistors reduce delay linearly.

Can the MP8005DF-LF-Z be used in non-isolated buck configurations?

Yes - the MP8005DF-LF-Z supports both isolated (flyback, forward) and non-isolated (buck, buck-boost) topologies. Its COMP and VFB pins interface directly with standard voltage-mode error amplifiers, and MAINGATE/SYNCGATE drive external high- and low-side FETs without transformer coupling requirements.

What is the purpose of the two RTN pins (12 and 13), and how should they be routed?

Pins 12 and 13 are electrically identical RTN terminals, designed to reduce current density and improve thermal performance. Both must be connected to the same low-impedance ground plane, preferably with separate 10-mil+ traces converging at a single star point near the exposed pad to minimize voltage drop and ensure accurate ISENSE measurement.

Does the MP8005DF-LF-Z support IEEE 802.3at (PoE+) or 802.3bt (PoE++)?

No - the MP8005DF-LF-Z is strictly IEEE 802.3af (Type 1) compliant. It lacks the higher-class detection signatures, extended voltage range (>57V), and dual-signature classification required for 802.3at (Class 4–5) or 802.3bt (Class 6–8). For PoE+, consider MPS's MP8010 or MPQ8018 families.

How is the PG (Power Good) signal debounced, and what is its logic polarity?

The PG pin is an active-low, open-drain output with built-in 75–225μs deglitch filtering on both rising and falling edges. It asserts low only after VDD charges to within 1V of the input potential and remains low during normal operation - providing clean sequencing signals to downstream regulators or microcontrollers without external RC networks.