Monolithic Power Systems Inc. MP8008GV-P

Overview

MP8008GV-P from Monolithic Power Systems is a fully integrated IEEE 802.3af/at-compliant Powered Device (PD) interface with peak-current-mode flyback controller. It integrates a 100V/0.48Ω hot-swap MOSFET, supports 120mA inrush and 840mA operational current limiting, delivers 12V/1A gate drive, and operates in QFN-28 (4mm×5mm) package for PoE-powered security cameras and WLAN access points.

For engineers reviewing the MP8008GV-P datasheet, MP8008GV-P pinout, MP8008GV-P application, or MP8008GV-P equivalent, key selection criteria include IEEE 802.3at Type-2 classification support, programmable 30–400kHz switching frequency, pulse-skipping light-load efficiency, and dual-input (PSE + wall adapter) operation with T2P/PG status signaling.

Technical Context

The MP8008GV-P implements a dual-path PD interface: detection (24.9kΩ signature), 1-event or 2-event classification (up to Class 4), and adaptive inrush-to-operational current transition (120mA → 840mA at VRTN < 1.2V). Its flyback controller features cycle-by-cycle current sensing via ISENSE, OVP monitoring on FB (1.438V threshold), and soft-start controlled by SS capacitor.

It supports auxiliary power detection via AUX pin with –2.3V reference relative to VDD, enabling seamless switchover between PoE and wall adapter inputs. Thermal shutdown (160°C) and hiccup-mode overload protection (17.8μA SS discharge) are hardware-asserted without external components.

Key Specifications

Pinout & Package

MP8008GV-P is housed in a thermally enhanced QFN-28 (4mm × 5mm, 0.5mm pitch) package with exposed thermal pad (EP) connected to VSS. Pin 1 is marked by dot; pins 4,14,15,16,17,22,28 are NC and must be tied to GND in layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD interface with flyback controller applications.

Compared with LT4275AIMSE#PBF and TPS23754PWPR, MP8008GV-P uniquely combines 2-event classification, AUX-based adapter switchover, and pulse-skipping-reducing component count by 7 and enabling single-chip 25.5W PoE+ systems with zero-firmware power management.

Availability

MP8008GV-P is available at Aetrix Electronics and suitable for security cameras, WLAN access points, IoT gateways, and video telephones requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for MP8008GV-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with focus on efficiency, integration, and thermal robustness.

The MP8008 product line delivers single-chip PoE PD solutions targeting IEEE 802.3af/at compliance, minimizing external components while supporting dual-input (PSE + adapter) operation for mission-critical edge devices.

FAQ

What is the function of the AUX pin, and how is it configured for wall adapter detection?

The AUX pin detects wall adapter presence by comparing VDD–AUX to a –2.3V internal reference. When VDD–AUX exceeds 2.3V, the IC disables the hot-swap MOSFET and CLASS functions, asserts PG, and pulls T2P low. A resistor divider from VDD to the adapter's negative terminal sets the detection threshold per Equation (1) in the datasheet; DAPD1/DAPD2 diodes prevent backfeed between sources.

How does the MP8008GV-P handle 2-event classification for IEEE 802.3at Type-2 PSEs?

During 2-event classification, the PSE applies voltage in the 14.5–20.5V range (first classification), then drops to 6.9–10.1V (first mark event), repeats the sequence (second classification + second mark event), and finally powers up. The MP8008GV-P draws ~40.4mA in classification (RCLASS = 28.7Ω) and 0.5–2mA during mark events, enabling unambiguous Class 4 identification by Type-2 PSEs.

Can the MP8008GV-P operate without an external MOSFET, or is it strictly a controller?

The MP8008GV-P integrates a 100V/0.48Ω hot-swap MOSFET for the PD interface but requires an external N-channel MOSFET for the flyback power stage. The GATE pin drives this external FET; no internal power switch exists for the flyback primary side. This architecture enables >10A output current capability while maintaining thermal separation between PD and DC/DC sections.

What protections are implemented in hardware, and which require external components?

Hardware protections include overvoltage (FB pin), overload/short-circuit (ISENSE threshold), thermal shutdown (160°C), and UVLO (37.5V turn-on/31V turn-off). No external components are needed for these. External components required: RDET (24.9kΩ), RCLASS (e.g., 28.7Ω), RT (for frequency), SS capacitor (soft-start/hiccup timing), and flyback transformer/MOSFET/output rectifier/filter.

Is the MP8008GV-P compatible with legacy 802.3af PSEs, and how is backward compatibility ensured?

Yes - the MP8008GV-P fully complies with IEEE 802.3af detection (24.9kΩ signature), classification (Classes 0–3), and inrush/operational current limits. It automatically operates in 1-event mode with 802.3af PSEs and escalates to 2-event only when a Type-2 PSE signals the mark event sequence. No configuration change is needed; behavior is determined solely by PSE voltage sequencing.

What is the purpose of the T2P pin, and how should it be interfaced with system logic?

T2P is an open-drain output that pulls low to VSS when a Type-2 PSE or wall adapter is detected. It provides real-time status to the host MCU or FPGA without polling. Interface requires a pull-up resistor (typically 10kΩ to 3.3V); logic-high = no Type-2 source, logic-low = confirmed Type-2 PSE or adapter active. It remains asserted during normal operation once detected.

How is the switching frequency set, and what is the impact of RT resistor tolerance on accuracy?

Switching frequency is set by connecting a resistor from RT to GND. For example, RT = 6.81kΩ yields 337kHz (typ). Frequency tolerance depends on RT resistor tolerance and internal oscillator variation: ±5% typical over temperature and process. Use 1% metal-film resistors for EMI-critical designs; synchronization via EN/SYNC eliminates jitter accumulation across multiple units.