Monolithic Power Systems Inc. MP8008GV-Z

Overview

MP8008GV-Z from Monolithic Power Systems is a fully integrated IEEE 802.3af/at-compliant Powered Device (PD) interface with peak-current-mode flyback controller. It delivers PoE power conversion for up to 25.5W Type-2 applications, features a 100V/0.48Ω integrated hot-swap MOSFET, 120mA inrush current limit, 840mA operational current limit, and programmable 30–400kHz switching frequency-used in security cameras and WLAN access points.

For engineers reviewing the MP8008GV-Z datasheet, MP8008GV-Z pinout, MP8008GV-Z application, or MP8008GV-Z equivalent, key selection criteria include PD classification compliance (Type-1/Type-2), RTN-based current limiting behavior, AUX-driven wall-adapter detection logic, PG-to-EN/SYNC auto-start sequencing, and QFN-28 package thermal performance under sustained 12V/2.1A flyback loads.

Technical Context

The MP8008GV-Z implements dual-path power management: its PD interface handles IEEE 802.3af/at detection (24.9kΩ signature), 2-event classification (Class 0–4 via RCLASS), and 100V hot-swap control with 120mA/840mA current limits referenced to RTN. Simultaneously, its flyback controller supports isolated/non-isolated topologies using ISENSE for cycle-by-cycle current sensing and FB for OVP monitoring at 1.438V threshold.

Control architecture integrates pulse-skipping mode below 0.95V COMP voltage for light-load efficiency, soft-start via SS capacitor timing, and synchronized operation via EN/SYNC input accepting external clocks from 80–400kHz. Protection includes overload (OLP), short-circuit (SCP at 350mV ISENSE), over-voltage (OVP at 1.438V FB), and thermal shutdown at 160°C with 20°C hysteresis.

Key Specifications

Pinout & Package

MP8008GV-Z is housed in a thermally enhanced QFN-28 (4mm × 5mm) package with exposed thermal pad (EP), optimized for PoE PD board layouts requiring low profile and high power density. Pin 1 is marked by dot; NC pins (4,14,15,16,17,22,28) must be connected to GND per layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD interface with flyback controller applications.

Compared with LT4275AIMSE#PBF and TPS23754PWPR, MP8008GV-Z uniquely combines IEEE 802.3at Type-2 support, programmable 30–400kHz flyback control with synchronization, and seamless wall-adapter arbitration in a compact QFN-28 package-reducing total solution size by ≥35% versus discrete PD + controller approaches.

Availability

MP8008GV-Z is available at Aetrix Electronics and suitable for security cameras, WLAN access points, video telephones, and IoT gateways requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for MP8008GV-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with core expertise in DC/DC conversion, motor drivers, and PoE solutions.

The MP8008 product line targets IEEE 802.3af/at PoE-powered devices needing integrated front-end interface and flyback control-designed to minimize external components and accelerate time-to-market for networked endpoints.

FAQ

What is the maximum input voltage the MP8008GV-Z can withstand on the VDD pin?

The absolute maximum VDD-to-VSS voltage is +100V, with recommended operating range of 35V to 57V per IEEE 802.3at specifications. Exceeding 57V may trigger UVLO shutdown or damage internal structures; sustained operation above 57V violates PoE standards and is not supported.

How does the MP8008GV-Z handle simultaneous PoE and wall-adapter power sources?

When VDD–AUX exceeds 2.3V, the IC disables the hot-swap MOSFET and CLASS functions, asserts T2P low, and enables PG-effectively prioritizing wall-adapter power. A Schottky diode (DAPD2) blocks reverse current from adapter to PSE, ensuring source isolation per Figure 4 in the datasheet.

Can the MP8008GV-Z support non-isolated flyback (buck-derived) topologies?

Yes. ISENSE pin detects topology during startup: floating ISENSE selects isolated mode; connecting ISENSE to GND configures non-isolated operation. In non-isolated mode, FB monitors output directly and COMP drives the error amplifier for standard buck-derived regulation.

What is the purpose of the T2P pin, and how is it used in system design?

T2P is an open-drain output that pulls low to VSS when a Type-2 PSE or wall adapter is detected. It serves as a hardware status flag for microcontrollers or FPGAs to enable feature sets (e.g., higher-power modes) or log power-source events without software polling.

Does the MP8008GV-Z require external components for IEEE 802.3af/at compliance?

Yes-external components include: 24.9kΩ resistor (VDD–DET), RCLASS resistor (e.g., 28.7Ω for Class 4), RT resistor (for frequency setting), SS capacitor (soft-start timing), and flyback transformer/MOSFET/output rectifier/filter. The IC integrates all active PD interface and controller functions, minimizing BOM count.

How does the current-limit transition from inrush to operational mode occur?

At power-up, the IC limits RTN current to 120mA until VRTN falls below 1.2V, then transitions to 840mA after 100ms delay (TDELAY). If VRTN rises above 10V for >1ms or exceeds 20V, the limit reverts to 120mA and PG drops low-preventing thermal runaway during sustained overload.

Is the MP8008GV-Z compatible with legacy 802.3af PSEs?

Yes. It supports full 1-event classification for Classes 0–3 per IEEE 802.3af and automatically negotiates lower power levels (≤15.4W) when connected to Type-1 PSEs. Classification current values match Table 1 in the datasheet, ensuring interoperability without configuration changes.