Monolithic Power Systems Inc. MP8009GV-P

Overview

MP8009GV-P from Monolithic Power Systems is a fully integrated IEEE 802.3af/at compliant powered device (PD) interface with embedded flyback/forward controller. It integrates a 100V, 0.48Ω hot-swap MOSFET, supports 120mA inrush and 840mA operational current limiting, delivers primary-side regulation (PSR) for flyback and secondary-side regulation (SSR) for active-clamp forward topologies, and operates at 250kHz fixed switching frequency - enabling compact, high-efficiency PoE-powered security cameras and WLAN access points.

For engineers reviewing the MP8009GV-P datasheet, MP8009GV-P pinout, MP8009GV-P application, or MP8009GV-P equivalent, this page provides verified technical context, validated pin functions, topology-specific design meanings, real-world application constraints, and confirmed alternative options for PoE PD front-end design.

Technical Context

The MP8009GV-P implements dual-mode regulation control: PSR mode uses the FB pin as error amplifier output with sensing winding feedback, while SSR mode disables internal EA and repurposes FB solely for over-voltage protection. MODE pin configuration (floating = PSR; grounded via resistor = SSR) directly selects regulation architecture and sets dead-time between GATE and SYNC drivers.

Its PD interface executes full 802.3af/at compliance including 1-event/2-event classification (via CLASS pin resistor), detection (DET pin with 24.9kΩ pull-up), and thermal shutdown at 150°C with 20°C hysteresis. The 2A GATE and 0.8A SYNC drivers support N- and P-channel MOSFETs meeting QG >17.5nC (N) and >5nC (P) thresholds for active-clamp forward OVP accuracy.

Key Specifications

Pinout & Package

MP8009GV-P is housed in a thermally enhanced QFN-28 (4mm × 5mm) package with an exposed thermal pad connected to RTN/VSS for optimal power dissipation. Pin 1 is located at the top-left corner of the top view, with pins numbered counter-clockwise.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD interface with integrated DC/DC controller applications.

Compared with LT4275AIMSE#PBF and TPS23754PWPR, MP8009GV-P uniquely integrates full 802.3af/at compliance, dual-mode regulation (PSR/SSR), and active-clamp forward support in one QFN-28 package - reducing total solution size by >40% and eliminating optocoupler dependency.

Availability

MP8009GV-P is available at Aetrix Electronics and suitable for security cameras, WLAN access points, video telephones, and IoT gateways requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for MP8009GV-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of expertise in DC/DC converters, PoE solutions, and motor drivers.

The MP8009 product line targets space-constrained, high-efficiency PoE-powered endpoints - designed to replace multi-chip PD + controller solutions with a single IC supporting both flyback and active-clamp forward topologies.

FAQ

What is the maximum PoE input voltage supported by MP8009GV-P?

The MP8009GV-P supports PoE input up to 57V, covering the full IEEE 802.3at Type 2 specification. Its VDD absolute maximum rating is +100V, and PD UVLO turn-on threshold is 37.5V (typical), ensuring reliable startup across the entire 802.3at range while tolerating transient overvoltage events.

Can MP8009GV-P operate in both flyback and forward topologies simultaneously?

No - MP8009GV-P operates in either PSR flyback or SSR active-clamp forward mode, selected by the MODE pin configuration. Floating MODE enables PSR flyback; grounding MODE via resistor configures SSR operation. The IC cannot execute both topologies concurrently due to mutually exclusive feedback and driver timing requirements.

How does the AUX pin enable wall adapter detection?

The AUX pin monitors the voltage difference between VDD and the wall adapter ground. When VDD – AUX exceeds 2.3V, the IC disables the hot-swap MOSFET and CLASS functions, forcing T2P and PG active - signaling adapter presence. This allows seamless switchover between PoE and auxiliary power without external logic.

What is the minimum MOSFET gate charge required for active-clamp forward operation?

For accurate OVP in active-clamp forward mode, the MP8009GV-P requires an N-channel MOSFET with QG >17.5nC and a P-channel MOSFET with QG >5nC. These thresholds ensure sufficient gate drive energy for precise OVP triggering without false trips during transient load steps.

Does MP8009GV-P include built-in EMI reduction features?

Yes - MP8009GV-P incorporates frequency dithering that modulates the 250kHz switching frequency to spread spectral energy. This reduces peak EMI amplitudes, easing compliance with FCC Part 15 and CISPR-32 conducted/radiated emission limits without requiring additional external filtering components.

How is thermal performance managed in the QFN-28 package?

The QFN-28 package features an exposed thermal pad electrically and thermally connected to RTN/VSS. Designers must solder this pad to a large PCB copper pour tied to system ground, achieving θJA ≈ 37°C/W. Combined with 150°C thermal shutdown and 20°C hysteresis, this ensures sustained operation in sealed enclosures up to +85°C ambient.

Is the FB pin used for regulation in both PSR and SSR modes?

No - in PSR mode, FB serves as the error amplifier output and receives feedback from the auxiliary winding to regulate output voltage. In SSR mode, the internal EA is disabled; FB is repurposed solely for over-voltage protection monitoring, and regulation is handled by the secondary-side controller loop.