Monolithic Power Systems Inc. MP8017GL-P

Overview

MP8017GL-P from Monolithic Power Systems is an IEEE 802.3af-compliant PoE powered device (PD) IC with integrated active-clamp flyback controller, 100V/0.5Ω hot-swap MOSFET, and dual regulation modes (PSR/SSR). It delivers up to 13W isolated output power in a QFN-19 (3mm×4mm) package and targets compact security cameras, VoIP phones, WLAN access points, and IoT edge nodes requiring single-chip PoE front-end integration.

For engineers reviewing the MP8017GL-P datasheet, MP8017GL-P pinout, MP8017GL-P application, or MP8017GL-P equivalent, this page provides verified technical context on PSR/SSR topology selection, PoE detection/classification compliance, thermal protection behavior, and real-world efficiency vs. load current at 37–57V input.

Technical Context

The MP8017GL-P implements a dual-mode active-clamp flyback architecture: in PSR mode, it regulates output voltage via primary-side sensing without auxiliary winding, using VDIODE compensation and FB ramp control; in SSR mode, it accepts optocoupler feedback through COMP while disabling internal error amplifier and configuring FB as OVP threshold pin. Both modes share the same 0.37Ω LS-FET and 0.75Ω HS-FET switches.

Its PD interface fully executes IEEE 802.3af detection (1.5V turn-on, 11V turn-off), classification (configurable 2–40.4mA via CLASS resistor), inrush limiting (120mA), and 100V hot-swap FET control - all coordinated by internal state machine with hiccup-mode OLP/OVP/OTP protection and frequency dithering (±6%) for EMI reduction.

Key Specifications

Pinout & Package

MP8017GL-P is housed in a thermally enhanced QFN-19 (3mm × 4mm) package with exposed thermal pad (PGND-connected), optimized for high-power density PoE PD designs. Pin functions are validated per MPS MP8017 Rev. 1.1 datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD applications.

Compared with LT4275AIMSE#PBF and TPS23753APWR, MP8017GL-P uniquely integrates active-clamp topology, dual PSR/SSR regulation, and full 13W capability in one QFN-19 package - reducing total solution size by >30% and eliminating external clamp components.

Availability

MP8017GL-P is available at Aetrix Electronics and suitable for security camera modules, VoIP terminal designs, and industrial IoT gateways requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.

Supply support for MP8017GL-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of leadership in DC/DC converters, PoE solutions, and motor drivers.

The MP8017GL-P belongs to MPS's IEEE-compliant PoE PD product line, engineered specifically for space-constrained, isolated 13W applications where integration, efficiency, and thermal robustness are critical - such as smart building endpoints and edge AI sensors.

FAQ

What PoE standards does MP8017GL-P support?

MP8017GL-P is fully compliant with IEEE 802.3af (Type 1) for detection, classification, inrush, and operational current limits. It also supports Class 4 operation per IEEE 802.3at (Type 2) when paired with a compatible PSE, enabling up to 25.5W power draw with appropriate external circuitry.

How do I configure primary-side versus secondary-side regulation?

PSR mode is enabled by connecting FB to SW and leaving COMP floating; SSR mode requires connecting COMP to optocoupler cathode and configuring FB as OVP pin via SW–FB resistor or floating. M/D pin voltage level selects between modes per Table 2 in the datasheet.

Can MP8017GL-P operate without an external optocoupler?

Yes - in PSR mode, MP8017GL-P regulates output voltage using primary-side sensing and VDIODE compensation, eliminating the need for optocoupler, TL431, or auxiliary winding. Optocoupler is only required for SSR mode to achieve tighter output tolerance.

What is the purpose of the SNBR pin?

The SNBR pin connects to the active-clamp snubber capacitor and controls zero-voltage switching of the HS-FET. When VSNBR–VBUS exceeds 1.5V, the internal SYNC FET discharges the capacitor, recovering energy and improving efficiency over traditional clamp diodes.

Does MP8017GL-P include built-in EMI mitigation features?

Yes - it incorporates frequency dithering (±6% spread spectrum at 9kHz) to reduce peak conducted and radiated emissions. Combined with active-clamp ZVS operation and optimized gate drive, it meets CISPR 32 Class B requirements without additional filtering components.

How is thermal protection implemented?

MP8017GL-P monitors junction temperature and triggers thermal shutdown at 150°C with 20°C hysteresis. After shutdown, it enters hiccup mode with an 80–100ms cool-down timer before attempting automatic restart - preventing thermal runaway during sustained overload.

What is the minimum external component count for a functional PoE PD?

A minimal working configuration requires: 1× 24.9kΩ DET resistor, 1× CLASS resistor, 1× FSW resistor, 1× SS capacitor, 1× VCC bypass cap (≥2.2µF), 1× CP capacitor (0.01–0.22µF), 1× BST capacitor (0.22µF), plus transformer, output rectifier, and output caps - totaling <15 passive components.