Monolithic Power Systems Inc. MP8030GQJ-Z

Overview

MP8030GQJ-Z from Monolithic Power Systems is a fully integrated IEEE 802.3af/at/bt-compliant PoE powered device (PD) interface with embedded flyback/forward DC/DC controller. It integrates a 100V hot-swap MOSFET (R_ON = 0.35Ω), dual gate drivers (GATE1, GATE2), automatic classification, and maintain power signature (MPS) functionality. Designed for ≤51W PoE PDs or >51W designs with external FETs, it supports security cameras, VoIP phones, and WLAN access points.

For engineers reviewing the MP8030GQJ-Z datasheet, MP8030GQJ-Z pinout, MP8030GQJ-Z application, or MP8030GQJ-Z equivalent, key selection criteria include IEEE 802.3bt compliance up to Class 8, PSR/SSR topology flexibility, 250kHz switching frequency, thermal shutdown at 150°C, and QFN-32 (5mm×6mm) package with exposed thermal pad.

Technical Context

The MP8030 implements a dual-domain architecture: a PoE PD interface handling detection, classification, MPS, priority arbitration (PRI), and PSE type indication (TYP1/TYP2/BT), plus a programmable DC/DC controller supporting PSR flyback, SSR flyback, and SSR active-clamp forward topologies. Its MODE pin configures regulation mode and dead time, while CS sets frequency dithering and output compensation.

Protection logic includes hiccup-mode OLP (4.8ms on / 340ms off), SCP, OVP (125% V_REF), and thermal shutdown with 20°C hysteresis. The R_MPS pin delivers a regulated 24V pulse for MPS, with duty cycle configurable via DUTY pin (6–17%) based on PSE type and external resistor.

Key Specifications

Pinout & Package

MP8030GQJ-Z uses a thermally enhanced QFN-32 (5mm × 6mm) package with an exposed copper thermal pad (Pin 32 AUX is NC; Pad must be soldered to PCB ground plane). Pin functions are validated per MP8030 Rev. 1.1 datasheet, with dedicated grounds (Pin 11 for DC/DC, Pin 29 for PD interface) requiring separate local decoupling before connection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PoE PD interface applications.

Compared with LT4275AIMSE#PBF and MAX5974DETE+T, MP8030GQJ-Z uniquely integrates full 802.3bt compliance, dual gate drivers (GATE1/GATE2), and flexible PSR/SSR/active-clamp forward control-enabling single-chip 90W PoE PD designs with minimal external components and no optocoupler dependency.

Availability

MP8030GQJ-Z is available at Aetrix Electronics and suitable for security cameras, VoIP phones, and WLAN access points requiring stable component supply across extended product lifecycles and industrial temperature operation.

Supply support for MP8030GQJ-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of innovation in DC/DC converters, PoE solutions, and motor drivers.

The MP8030 belongs to MPS's PoE PD Interface + Controller product line, engineered to consolidate IEEE-compliant power extraction and high-efficiency DC/DC conversion into a single QFN package for space-constrained edge devices.

FAQ

What is the maximum PoE power class supported by MP8030GQJ-Z?

MP8030GQJ-Z supports IEEE 802.3bt Type 3 and Type 4, enabling Class 5–8 operation (up to 90W delivered power). Its automatic classification engine negotiates power level with the PSE across three class events, and its internal 100V hot-swap MOSFET handles ≤51W directly; external FETs driven by GATE1 extend capability beyond that.

How does the MP8030GQJ-Z implement maintain power signature (MPS) without external timers?

The MP8030GQJ-Z generates MPS autonomously using its R_MPS pin, which outputs a regulated 24V pulse with user-configurable duty cycle (6–17%) based on DUTY pin voltage. No external RC network or microcontroller is needed-the IC monitors load current and triggers MPS when falling below 36mA, maintaining IEEE 802.3bt compliance during low-power states.

Can MP8030GQJ-Z operate in both PSR and SSR modes simultaneously?

No-MODE pin selects either PSR (primary-side regulation) or SSR (secondary-side regulation) at power-up; the setting is latched and cannot be dynamically changed. PSR mode uses FB for regulation and COMP as EA output; SSR mode disables the internal EA and repurposes FB solely for OVP, requiring external feedback circuitry.

What thermal management is required for continuous 51W operation?

At 51W input (57V × 0.9A), the MP8030GQJ-Z dissipates ~2.1W in the internal MOSFET. With θ_JA = 32°C/W on a 4-layer EVB, junction rise is ~67°C above ambient. A 200mm² exposed thermal pad connected to ≥2oz internal ground planes and ≥4 thermal vias is mandatory to maintain T_J ≤ 125°C at 70°C ambient.

Does MP8030GQJ-Z require an external current-sense resistor for the internal hot-swap FET?

No-the internal hot-swap MOSFET's current limit is set by the ILIM pin voltage (0.8V or 1.0V thresholds), not by an external sense resistor. However, SENSE pin is used only when driving an external N-channel MOSFET (GATE1 path); for internal-FET-only operation, SENSE must be tied to VDD.

How is adapter supply (VADP) prioritized relative to PoE input?

Priority is controlled by the PRI pin: internally pulled high to 5V, so PoE (VDD) has default priority. Pulling PRI low forces the IC to select VADP as primary supply-enabling seamless failover. GATE2 activates only when VADP exceeds 8.3V UVLO, and PG remains asserted if either source is valid.

Is the QFN-32 package lead-free and RoHS compliant?

Yes-MP8030GQJ-Z is lead-free, halogen-free, and fully compliant with EU RoHS Directive 2011/65/EU. The top marking includes MPS prefix, year/week code, and lot number; moisture sensitivity level is MSL 2 per J-STD-020.