Monolithic Power Systems Inc. MPQ1918GQE-AEC1-P

Overview

MPQ1918GQE-AEC1-P from Monolithic Power Systems is a 100V, AEC-Q100 Grade 1 qualified half-bridge gate driver optimized for enhancement-mode GaN FETs and low-threshold N-channel MOSFETs. It delivers independent high-side (HS) and low-side (LS) TTL-compatible PWM inputs, 0.27Ω/1.2Ω sink/source pull-down/up resistance, <30ns propagation delay, and 1.5ns typical delay matching - enabling >1MHz switching in automotive DC/DC converters and Class-D audio amplifiers.

For engineers reviewing the MPQ1918GQE-AEC1-P datasheet, MPQ1918GQE-AEC1-P pinout, MPQ1918GQE-AEC1-P application, or MPQ1918GQE-AEC1-P equivalent, key selection criteria include bootstrap-clamped VBST-SW (≤106% VCC), -40°C to +125°C operating junction temperature, dual VCC pins (pins 10 & 14), and wettable-flank FCQFN-14 package compatibility with automated optical inspection.

Technical Context

The MPQ1918GQE-AEC1-P integrates independent level-shifted HS and LS drivers with dedicated source/sink outputs (HGP/HGN/LGP/LGN) enabling discrete gate loop impedance tuning for asymmetric turn-on/turn-off control. Its bootstrap charging logic activates only when PWML = 1, preventing VBST-SW from exceeding VCC and safeguarding GaN FETs against gate overvoltage.

It features dual UVLO monitoring: VCC UVLO (3.7–4.5V rising threshold, 350mV hysteresis) and VBST-SW UVLO (80–92% of VCC, 7% hysteresis), ensuring safe operation under bus transients up to 100VDC on SW and 108V peak. Thermal shutdown triggers at 170°C with 30°C hysteresis.

Key Specifications

Pinout & Package

MPQ1918GQE-AEC1-P uses an FCQFN-14 (3mm × 3mm) package with wettable flanks for solder joint inspection. Dual VCC pins (10 & 14) and separate AGND (9) / PGND (11) grounds support clean signal/power separation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge GaN/MOSFET driver applications.

Compared with LM5113-Q1 and UCC27624, MPQ1918GQE-AEC1-P uniquely integrates GaN-safe bootstrap clamping, AEC-Q100 Grade 1 qualification, and independent gate outputs - eliminating external protection components and simplifying layout for >1MHz automotive power stages.

Availability

MPQ1918GQE-AEC1-P is available at Aetrix Electronics and suitable for automotive DC/DC converters, Class-D audio amplifiers, and high-voltage power modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MPQ1918GQE-AEC1-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan and global manufacturing partnerships.

The MPQ1918 product line targets high-frequency, high-reliability gate driving for GaN-based automotive power conversion - emphasizing integrated safety features, AEC-Q100 compliance, and layout-optimized packaging for EMI-sensitive environments.

FAQ

What is the maximum recommended switching frequency for MPQ1918GQE-AEC1-P?

The MPQ1918GQE-AEC1-P supports operation up to several MHz, with characterization data confirming stable 1MHz performance in typical application circuits using EPC2218 GaN FETs. Minimum gate pulse width is 15ns, enabling practical use at ≥800kHz with adequate dead time. Layout parasitics and gate charge determine actual upper limit in end systems.

How does the internal bootstrap clamp protect GaN FETs?

The MPQ1918GQE-AEC1-P clamps VBST-SW to 106% of VCC via internal circuitry, preventing gate-source overvoltage during fast transients. Unlike conventional bootstraps, its charging logic activates only when PWML = 1, ensuring VBST never exceeds VCC - directly addressing the ±6V absolute maximum rating of enhancement-mode GaN FETs.

Why are there two VCC pins (10 and 14) on the MPQ1918GQE-AEC1-P?

Pins 10 and 14 are both VCC inputs, each requiring a dedicated 100nF low-ESL/ESR MLCC decoupling capacitor to AGND and PGND respectively. This dual-pin design reduces effective supply impedance, maintains stable gate drive voltage during 5A peak sink currents, and separates noise-sensitive logic supply from power-stage return paths.

Can MPQ1918GQE-AEC1-P drive silicon MOSFETs as well as GaN FETs?

Yes - the MPQ1918GQE-AEC1-P is specified for both enhancement-mode GaN FETs and low-threshold N-channel MOSFETs. Its 0.27Ω pull-down resistance and 1.2Ω pull-up resistance are optimized for fast GaN switching but remain compatible with standard Si MOSFETs; gate loop resistors may be adjusted to match required dV/dt and EMI targets.

What is the purpose of the separate AGND and PGND pins?

AGND (pin 9) serves as the reference for PWM inputs and internal logic, while PGND (pin 11) is the power ground for LS gate drive and PWM outputs. They must be connected via a single-point 0Ω resistor on the PCB bottom layer to prevent noise coupling from high di/dt gate currents into sensitive input circuitry - a critical layout requirement per MPS application note.

Does MPQ1918GQE-AEC1-P include thermal shutdown protection?

Yes - it incorporates thermal shutdown at 170°C junction temperature with 30°C hysteresis. When triggered, the device disables both HS and LS outputs until temperature falls below 140°C. This protection is fully characterized and guaranteed across the –40°C to +125°C operating range, supporting automotive under-hood reliability requirements.