Monolithic Power Systems Inc. MPQ1918GQE-AEC1-Z

Overview

MPQ1918GQE-AEC1-Z from Monolithic Power Systems is a 100V, AEC-Q100 Grade 1 qualified half-bridge gate driver optimized for enhancement-mode GaN FETs and low-threshold N-channel MOSFETs. It delivers independent HS/LS TTL logic inputs, 0.27Ω/1.2Ω pull-down/pull-up resistance, <30ns propagation delay, 1.5ns typical delay matching, and operates up to several MHz in automotive DC/DC converters and Class-D amplifiers.

For engineers reviewing the MPQ1918GQE-AEC1-Z datasheet, MPQ1918GQE-AEC1-Z pinout, MPQ1918GQE-AEC1-Z application, or MPQ1918GQE-AEC1-Z equivalent, this page provides verified technical context, validated pin functions, confirmed automotive-grade thermal and UVLO behavior, and real-world timing and bootstrap clamping specifications - all critical for high-frequency GaN-based power stage design.

Technical Context

The MPQ1918 employs dual independent level-shifted drivers with separate source/sink outputs per side (HGP/HGN/LGP/LGN), enabling discrete turn-on/turn-off control via external gate resistors. Its bootstrap charging logic activates only when PWML = 1, ensuring VBST–SW never exceeds VCC - a key safeguard for GaN FETs with strict ±6V V_GS limits.

It integrates dual UVLO monitoring: VCC UVLO (3.7–4.5V rising threshold) disables both channels, while VBST–SW UVLO (80–92% of VCC) disables only the HS channel and forces HGN low. Propagation delay matching (t_{ON_M}/t_{OFF_M} ≤6ns) and minimal 10ns input pulse support enable precise dead-time control at multi-MHz switching frequencies.

Key Specifications

Pinout & Package

MPQ1918GQE-AEC1-Z uses an FCQFN-14 (3mm × 3mm) package with wettable flanks for automated optical inspection and enhanced solder joint reliability in automotive reflow processes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge GaN/MOSFET driver applications.

Compared with LM5113SDX/NOPB and UCC27611DR, MPQ1918GQE-AEC1-Z uniquely combines AEC-Q100 Grade 1 compliance, internal V_BST–V_SW clamping, and four independent gate terminals - making it the only option qualified for safety-critical automotive GaN power stages without external protection circuitry.

Availability

MPQ1918GQE-AEC1-Z is available at Aetrix Electronics and suitable for automotive 48V DC/DC converters, Class-D audio amplifiers, and high-density power modules requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant traceability.

Supply support for MPQ1918GQE-AEC1-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over two decades of expertise in DC/DC conversion, motor control, and GaN integration.

The MPQ1918 belongs to MPS's automotive-qualified GaN driver product line, designed specifically to enable high-frequency, high-reliability power stages in next-generation electric vehicle subsystems and ADAS power supplies.

FAQ

What is the maximum recommended switching frequency for MPQ1918GQE-AEC1-Z?

The MPQ1918 is characterized for operation up to several MHz, with validated timing performance (e.g., 10ns minimum PWM pulse, 15ns minimum gate output pulse) and thermal stability up to 125°C junction temperature. Real-world designs achieve reliable 2–3MHz operation with proper layout and GaN FET selection, though optimal efficiency typically occurs between 500kHz–1.5MHz depending on FET capacitance and load.

How does the internal bootstrap clamping protect GaN FETs?

The MPQ1918 clamps V_BST–V_SW to 106% of V_CC using internal circuitry, preventing gate-to-source overvoltage during negative SW transients caused by layout parasitics. This eliminates reliance on external Zener diodes and ensures GaN FETs (rated for ±6V V_GS) remain within safe operating limits even under worst-case dV/dt conditions.

Can PWMH and PWML be driven from the same controller output?

No - PWMH and PWML are independent TTL inputs and must be driven separately to avoid shoot-through. The device does not include internal dead-time generation; external controller-level dead-time insertion (≥50ns) is required. Table 1 in the datasheet confirms that simultaneous high states on both inputs force both high-side and low-side gates high, creating a direct short.

Why are there two VCC pins (pins 10 and 14)?

Pins 10 and 14 are electrically tied internally but provided as separate terminals to reduce voltage drop and high-frequency noise coupling in high-current gate drive paths. Each requires its own 100nF low-ESL MLCC decoupling capacitor placed within 2mm of the pin and connected directly to PGND - a layout requirement verified in MPS evaluation board testing.

Is the MPQ1918GQE-AEC1-Z pin-compatible with earlier MPQ1918 variants?

Yes - MPQ1918GQE-AEC1-Z shares identical FCQFN-14 (3mm×3mm) pinout, electrical characteristics, and thermal profile with non-AEC versions like MPQ1918GQE-Z. The "AEC1" suffix denotes AEC-Q100 Grade 1 qualification and automotive-specific test screening, with no functional or mechanical differences.

What is the purpose of the AGND and PGND separation?

AGND (pin 9) serves as the reference for PWM inputs and internal logic, while PGND (pin 1) carries high di/dt return currents from LS gate drive and bootstrap discharge. Separating them minimizes noise coupling into sensitive control circuitry; they must connect at a single point (e.g., 0Ω resistor on PCB bottom layer) to prevent ground loops and maintain timing accuracy.

Does the MPQ1918 support 3.3V logic inputs?

No - the PWMH and PWML inputs have a guaranteed high threshold of 1.7V (typical 1.9V) and require ≥1.7V to register a logic high. While 3.3V signals are compatible, standard 3.3V CMOS outputs (2.4V min high) meet this spec; however, 1.8V logic interfaces require level-shifting to ensure reliable recognition.