Monolithic Power Systems Inc. MPQ1923GRE-AEC1-P

Overview

MPQ1923GRE-AEC1-P from Monolithic Power Systems is an AEC-Q100 Grade 1 qualified, high-frequency N-channel MOSFET half-bridge gate driver with 100V switching node rating, 8A sink/7A source peak output current at 12V VDD, and <5ns propagation delay matching between high-side and low-side channels. It integrates a bootstrap diode, supports independent INH/INL control, and targets automotive motor drivers and telecom DC/DC converters.

For engineers reviewing the MPQ1923GRE-AEC1-P datasheet, MPQ1923GRE-AEC1-P pinout, MPQ1923GRE-AEC1-P application, or MPQ1923GRE-AEC1-P equivalent, key selection criteria include bootstrap voltage range (120V), UVLO thresholds (4.5V falling), rise/fall times (7.2ns/5.5ns into 1nF), TTL-compatible inputs, and QFN-10 (4mm×4mm) package with exposed thermal pad.

Technical Context

The MPQ1923GRE-AEC1-P implements dual independent gate drivers: a floating high-side channel (DRVH) referenced to SW with BST-supplied bias, and a grounded low-side channel (DRVL) referenced to VSS. Both channels feature matched propagation delays (<5ns) and separate under-voltage lockout (UVLO) monitoring of VDD and BST–SW differential voltage.

It uses internal logic to enforce shoot-through prevention via input timing constraints (minimum 50ns pulse width, tMON/tMOFF ≤5ns), while its integrated bootstrap diode eliminates external diode requirements in high-side bootstrap circuits operating up to 120V BST–SW.

Key Specifications

Pinout & Package

MPQ1923GRE-AEC1-P is housed in a thermally enhanced QFN-10 (4mm × 4mm) package with an exposed pad for PCB-level heat dissipation. The package complies with JEDEC MO-220, features 0.10mm max lead coplanarity, and requires IPC-2221-compliant conformal coating post-mounting.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with MPQ1923GR-AEC1, the MPQ1923GRE-AEC1-P offers additional NC pins for mechanical stability and marginally better thermal performance; versus LM5109BMMX/NOPB, it delivers automotive-grade reliability, integrated BST diode, and 8× higher peak current for demanding high-frequency motor control.

Availability

MPQ1923GRE-AEC1-P is available at Aetrix Electronics and suitable for automotive motor drivers, telecom power supplies, avionics DC/DC converters, and two-switch forward converters requiring stable component supply with AEC-Q100 qualification and high-speed gate drive capability.

Supply support for MPQ1923GRE-AEC1-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ1923-AEC1 product line delivers automotive-qualified half-bridge gate drivers optimized for high-frequency, high-reliability motor control and isolated DC/DC conversion in harsh environments.

FAQ

What is the maximum allowable bootstrap voltage (V_BST–V_SW) for MPQ1923GRE-AEC1-P?

The absolute maximum BST–SW voltage is +120V, with recommended operating limit at +100V. Exceeding 120V risks permanent damage to the internal bootstrap diode and high-side driver circuitry. The device includes BST–SW UVLO with 3.2V falling threshold to force DRVH low before reaching unsafe levels.

Does MPQ1923GRE-AEC1-P require external bootstrap diodes?

No. MPQ1923GRE-AEC1-P integrates a monolithic bootstrap diode with 0.9V forward voltage at 100μA and 1.2V at 100mA. This eliminates the need for external diodes, reduces PCB area, and improves reliability in high-vibration automotive environments.

How is shoot-through prevented in MPQ1923GRE-AEC1-P?

Shoot-through is prevented through strict input timing requirements: minimum 50ns pulse width (t_PW), and guaranteed t_MON/t_MOFF ≤5ns. Designers must implement external dead-time control in the PWM controller to ensure non-overlapping INH/INL signals - the IC does not generate dead time internally.

What is the thermal resistance (θ_JA) of the QFN-10 package?

The junction-to-ambient thermal resistance (θ_JA) is 47°C/W when mounted on a 4-layer JEDEC-standard PCB (JESD51-7). Effective thermal performance requires soldering the exposed pad to a solid VSS plane with ≥4 thermal vias, as specified in the PCB layout guidelines.

Can MPQ1923GRE-AEC1-P drive both MOSFETs simultaneously?

Yes - it supports simultaneous HS/LS drive for two-switch forward and active-clamp forward topologies. However, in half-bridge mode, INH and INL must be driven with alternating polarity and sufficient dead time to avoid shoot-through; simultaneous high states are not permitted.

Is the exposed thermal pad electrically connected internally?

Yes - the exposed pad is internally connected to VSS and must be soldered to the PCB's VSS plane. It serves both thermal and electrical functions: improving heat dissipation (θ_JC = 7°C/W) and lowering ground impedance for stable gate drive return paths.

What input logic family is compatible with INH and INL?

INH and INL accept TTL-compatible logic: VIH = 2.0–2.4V min, VIL = 0.8–1.2V max, with 600mV hysteresis. They are not CMOS-rail-to-rail; direct connection to 3.3V or 5V microcontrollers is safe, but 1.8V logic requires level translation.