Monolithic Power Systems Inc. MPQ1923GRE-AEC1-Z

Overview

MPQ1923GRE-AEC1-Z from Monolithic Power Systems is a high-frequency, AEC-Q100 Grade 1 qualified N-channel MOSFET half-bridge gate driver with 100V switching node rating, 8A sink/7A source peak output current, and <5ns HS/LS driver matching delay. It integrates a bootstrap diode, supports 5V–17V VDD operation, and is used in automotive motor drivers and telecom DC/DC converters.

For engineers reviewing the MPQ1923GRE-AEC1-Z datasheet, MPQ1923GRE-AEC1-Z pinout, MPQ1923GRE-AEC1-Z application, or MPQ1923GRE-AEC1-Z equivalent, key selection criteria include bootstrap voltage range (120V), propagation delay (20ns typ), UVLO thresholds (4.5V falling), thermal shutdown (165°C), and QFN-10 (4mm×4mm) package compatibility with exposed thermal pad.

Technical Context

The MPQ1923GRE-AEC1-Z implements independent TTL-compatible INH and INL inputs to control high-side and low-side N-MOSFET drivers with matched timing (<5ns skew). Its floating high-side driver uses bootstrap supply (VBST–SW up to 120V) and features integrated BST diode to eliminate external diode requirement.

UVLO protection operates separately on VDD (4.1–4.9V falling threshold) and BST–SW (1.4–4.6V falling threshold), forcing both DRVH and DRVL low during undervoltage. Thermal shutdown activates at 165°C with 25°C hysteresis, and the device sustains 100V SW node voltage with <50V/ns slew rate compliance.

Key Specifications

Pinout & Package

MPQ1923GRE-AEC1-Z is housed in a thermally enhanced QFN-10 (4mm × 4mm) package with exposed thermal pad. The package complies with JEDEC MO-220, supports reflow soldering per IPC/JEDEC J-STD-020, and requires PCB land pattern per MPS recommended layout (multiple vias to solid ground plane).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Compared with MPQ1923GRE-AEC1-Z, the MPQ1923GR-AEC1-Z offers identical performance in a smaller QFN-8 package but sacrifices pin flexibility, while the UCC27211DRCR lacks automotive qualification, integrated BST diode, and peak current capability - making it unsuitable for high-reliability 100V half-bridge designs requiring AEC-Q100 compliance.

Availability

MPQ1923GRE-AEC1-Z is available at Aetrix Electronics and suitable for automotive motor drivers, telecom half-bridge power supplies, and avionics DC/DC converters requiring stable component supply across extended temperature and long product lifecycles.

Supply support for MPQ1923GRE-AEC1-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with over 20 years of expertise in DC/DC converters, gate drivers, and motor control solutions.

The MPQ1923-AEC1 product line delivers AEC-Q100 Grade 1 half-bridge gate drivers optimized for high-frequency, high-voltage automotive and industrial power conversion - emphasizing timing precision, thermal robustness, and system-level reliability.

FAQ

What is the maximum allowable SW node voltage for MPQ1923GRE-AEC1-Z?

The MPQ1923GRE-AEC1-Z supports a continuous SW node voltage of –1V to +100V, with transient rating up to +120V for durations under 2µs. This enables use in 48V and 60V automotive systems and 100V telecom rectifiers without external clamping.

Does MPQ1923GRE-AEC1-Z require an external bootstrap diode?

No. The device integrates a bootstrap diode with forward voltage of 0.9V at 100µA, eliminating the need for an external diode and reducing component count and PCB area in half-bridge designs.

How does the dual UVLO protection function in MPQ1923GRE-AEC1-Z?

It provides independent under-voltage lockout on both VDD (4.1–4.9V falling threshold) and BST–SW (1.4–4.6V falling threshold). If either rail drops below its threshold, both DRVH and DRVL are forced low to prevent partial or erratic gate drive.

What is the thermal resistance of the QFN-10 package?

The QFN-10 (4mm×4mm) package has θ_JA = 47°C/W and θ_JC = 7°C/W when mounted on a 4-layer PCB per JESD51-7. Full thermal performance requires soldering the exposed pad to a solid ground plane with ≥4 thermal vias.

Can MPQ1923GRE-AEC1-Z drive SiC or GaN MOSFETs?

Yes - its 8A sink/7A source peak current, 7.2ns rise time into 1nF, and 100V SW rating make it compatible with discrete SiC and GaN FETs in hard-switched and resonant topologies up to 1MHz, provided gate loop inductance is minimized.

Is there a recommended minimum dead time between INH and INL signals?

MPS recommends ≥50ns minimum input pulse width (t_PW) and sufficient dead time to avoid shoot-through. Given <5ns driver matching, 100–200ns dead time is typical for 100V systems; exact value depends on MOSFET Q_g, layout parasitics, and bus voltage.

What is the purpose of the NC pins (5 and 6) in the QFN-10 package?

Pins 5 and 6 are no-connect terminals - not internally bonded and electrically isolated. They may be left unconnected or grounded for mechanical stability, but must not be used for signal routing or thermal conduction per MPS layout guidelines.