Monolithic Power Systems Inc. MPQ6528GVE-AEC1-P

Overview

MPQ6528GVE-AEC1-P from Monolithic Power Systems is an AEC-Q100 Grade 1 qualified H-bridge gate driver IC designed to control two independent N-channel MOSFET half-bridges across a 5V–60V input range. It integrates a regulated charge pump (VREG = 9.5–13V), bootstrap high-side drivers with trickle-charge for 100% duty cycle, and configurable dead time (700ns–5.7µs). Used in automotive brushed DC motor actuators requiring robust fault protection and thermal resilience up to +150°C junction temperature.

For engineers reviewing the MPQ6528GVE-AEC1-P datasheet, MPQ6528GVE-AEC1-P pinout, MPQ6528GVE-AEC1-P application, or MPQ6528GVE-AEC1-P equivalent, key selection criteria include VIN operating range, HS-FET bootstrap sustain capability at 100% duty, OCP threshold adjustability via OC_REF, and AEC-Q100 Grade 1 qualification for under-hood automotive use.

Technical Context

The MPQ6528 implements dual-phase H-bridge control using independent ENA/ENB enable inputs and PWMA/PWMB logic-driven PWM interfaces. Its internal charge pump generates VREG for LS-FET drivers while BSTA/BSTB pins support external bootstrap capacitors with integrated trickle-charge circuitry to maintain HS-FET gate voltage during continuous conduction.

Protection architecture includes three independent fault detection paths: UVLO (3.2–5V rising threshold), over-current via LSS shunt sensing (0.4–0.6V threshold), and VDS-based short-circuit detection referenced to OC_REF (0.125–2.4V). Fault status is reported through open-drain nFAULT, and recovery requires either nSLEEP assertion or VIN re-entry into UVLO window.

Key Specifications

Pinout & Package

MPQ6528GVE-AEC1-P is housed in a thermally enhanced wettable flank QFN-28 package (4mm × 5mm) with exposed GND pad on underside. The package supports automated optical inspection (AOI) and improves thermal dissipation in high-power motor drive layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar H-bridge gate driver applications.

Compared with TBD72004FTG and DRV8876NQPWR, MPQ6528GVE-AEC1-P uniquely combines wide 5V–60V operation, AEC-Q100 Grade 1 compliance, and trickle-charged bootstrap for 100% duty-making it the only option qualified for under-hood 48V mild-hybrid actuators requiring continuous holding torque.

Availability

MPQ6528GVE-AEC1-P is available at Aetrix Electronics and suitable for automotive door lock actuators, electric parking brake modules, and HVAC blower motor drivers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MPQ6528GVE-AEC1-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance power management ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ6528 belongs to MPS's automotive-grade gate driver product line, engineered specifically for AEC-Q100-compliant brushed DC motor control in harsh environments such as engine compartments and chassis-mounted actuators.

FAQ

What is the minimum recommended BST capacitor value for MPQ6528GVE-AEC1-P?

The minimum recommended BST capacitor is 0.1µF ceramic (X5R/X7R, 25V rating), placed between BSTA and SHA (and BSTB and SHB). This value ensures adequate charge transfer for typical gate charges ≤125nC while supporting 100% duty cycle via the internal trickle-charge circuit. Larger values up to 1µF improve margin but must not exceed 1µF to avoid startup issues.

Can MPQ6528GVE-AEC1-P drive both high-side and low-side MOSFETs simultaneously in synchronous rectification mode?

No. MPQ6528GVE-AEC1-P is an H-bridge gate driver with complementary phase control-not a synchronous buck controller. Its architecture enforces dead time between HS-FET turn-off and LS-FET turn-on (and vice versa) to prevent shoot-through. Simultaneous conduction is intentionally blocked by the internal timing logic and adjustable DT resistor.

How does the OC_REF pin affect short-circuit protection behavior?

The OC_REF pin sets the reference voltage for the VDS-based short-circuit comparator. When the sensed MOSFET drain-source voltage exceeds OC_REF, SCP triggers and latches off all gate outputs. OC_REF is externally programmable from 0.125V to 2.4V, allowing tailoring of trip sensitivity to MOSFET RDS(ON) and expected fault currents-e.g., 1V OC_REF corresponds to ~2A fault current for a 500mΩ MOSFET.

Is the exposed thermal pad on the QFN-28 package required to be soldered to PCB ground?

Yes. The exposed pad on the underside of the QFN-28 package must be soldered to a solid GND plane using ≥6 thermal vias (0.3mm diameter) to achieve specified θJA = 40°C/W. Leaving the pad unconnected degrades thermal performance by >30%, risks exceeding 150°C junction temperature under 2A load, and voids AEC-Q100 qualification compliance.

What happens to gate outputs during UVLO condition?

When VIN falls below the UVLO rising threshold (3.2–5V), all gate outputs (GHA, GHB, GLA, GLB) are forced into high-impedance state and internal logic resets. VREG is disabled, nFAULT is pulled low, and the device remains inactive until VIN rises above the UVLO threshold and completes the ~1ms start-up sequence-including VREG stabilization to >7.6V before output enable.

Does MPQ6528GVE-AEC1-P support 3.3V logic inputs?

Yes. The logic inputs (PWMA, PWMB, ENA, ENB, nSLEEP, nFAULT) accept 3.3V CMOS levels: VIH is guaranteed ≥2.0V and VIL ≤0.8V. Internal pull-down resistors (880kΩ) on all logic inputs except nSLEEP ensure defined states during power-up; nSLEEP has its own dedicated 1µA pull-down for deterministic sleep entry.

How is dead time calculated when using a 20kΩ resistor on the DT pin?

With a 20kΩ resistor from DT to GND, dead time is calculated as tDEAD(ns) = 60 × RDT(kΩ) = 60 × 20 = 1200ns (1.2µs). This value is verified in the Electrical Characteristics table (page 7) and confirmed in Application Information (page 15) as sufficient for 20kHz–30kHz PWM operation while minimizing body-diode conduction loss in inductive motor loads.