onsemi NP0640SCT3G
- Part No.:
- NP0640SCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP0640SCT3G.pdf
- Description:
- THYRISTOR 58V 100A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:7,258
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NP0640SCT3G from onsemi is a bidirectional thyristor surge protector (TSPD) designed for overvoltage protection in telecom line interfaces. It features 58 V peak off-state voltage (VDRM), 77 V breakover voltage (VBO), 4.0 V on-state voltage at 1 A, 150 mA holding current, and supports 150 A peak pulse current (2×10 µs waveform). It is used in central office and customer premises equipment to meet GR-1089-CORE and ITU-T K.20 compliance.
For engineers reviewing the NP0640SCT3G datasheet, pinout, applications, or equivalent options, key selection criteria include bidirectional clamping capability, SMB package compatibility, surge current rating under 2×10 µs and 10×160 µs waveforms, thermal resistance (90 °C/W), and RoHS-compliant lead-free construction.
Technical Context
The NP0640SCT3G operates as a voltage-triggered crowbar device: it remains high-impedance below VDRM (58 V), switches to low-impedance conduction above VBO (77 V), and latches until current falls below IH (150 mA). Its bidirectional symmetry enables single-device protection of AC-coupled telecom lines without polarity concerns.
It is rated for operation from −40 °C to +150 °C, with thermal resistance of 90 °C/W (Junction-to-Ambient, FR4 PCB per JESD51-3), and exhibits 84 pF typical capacitance at 1 MHz/2 Vdc bias - critical for preserving signal integrity in DSL and POTS applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | 58 V - Maximum repetitive off-state voltage before conduction; defines maximum steady-state line voltage tolerance. |
| VBO | 77 V - Breakover voltage at both polarities; triggers crowbar action during transient surges. |
| IH | 150 mA - Minimum current required to maintain conduction after triggering; ensures reliable latch-off during low-current recovery. |
| IPPS (2×10 µs) | 150 A - Peak non-repetitive surge current handling; meets GR-1089-CORE Level A surge immunity. |
| CO | 84 pF - Junction capacitance at 1 MHz/2 Vdc; low enough to avoid signal attenuation in voice-band and ADSL2+ interfaces. |
| RθJA | 90 °C/W - Thermal resistance on standard FR4 board; determines power derating and safe continuous surge duty cycle. |
| TJ Range | −40 °C to +150 °C - Operating junction temperature range; supports deployment in uncontrolled telecom cabinets and outdoor DSLAM enclosures. |
Pinout & Package
NP0640SCT3G is housed in an SMB (DO-214AA, Case 403C) surface-mount package with two terminals: MT1 and MT2. The device is symmetrical and bidirectional; either terminal may serve as anode or cathode depending on applied polarity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MT1 | Main Terminal 1 | One of two identical, interchangeable main terminals; connects to protected line (e.g., tip or ring in POTS). |
| MT2 | Main Terminal 2 | Second identical main terminal; completes bidirectional surge path; no gate or control pin present. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping | Enables single-device protection of AC-coupled telecom lines (e.g., POTS, xDSL) without external diodes or polarity management. |
| Low on-state voltage (4.0 V) | Minimizes power dissipation during surge conduction, reducing thermal stress and enabling compact PCB layout near line transformers. |
| 150 A 2×10 µs surge rating | Meets GR-1089-CORE Level A requirements for central office equipment, eliminating need for cascaded protection stages. |
| 84 pF capacitance | Preserves frequency response up to 2.2 MHz, supporting ADSL2+ and VDSL2 line interface designs without signal degradation. |
| Pb-free SMB package | Complies with RoHS Directive 2011/65/EU and supports reflow soldering per J-STD-020; footprint compatible with legacy DO-214AA layouts. |
Applications
| Central Office Line Card Protection | DSLAM Port Surge Suppression |
|---|---|
Use Scenario: Protecting analog line interface circuits in carrier-grade central office switches against lightning-induced surges and power cross events. IC Role / Device Role / Timing Role: Crowbar-type overvoltage protector placed between line transformer secondary and codec IC input. Use Value: Withstands 150 A (2×10 µs) surges while maintaining <4.0 V clamping voltage, preventing damage to downstream SLIC and codec components. |
Use Scenario: Securing individual VDSL2/ADSL2+ ports in multi-port DSL access multiplexers exposed to induced transients on outside plant wiring. IC Role / Device Role / Timing Role: Bidirectional TSPD mounted directly at RJ-11 connector, shunting surge energy before reaching line driver/receiver ICs. Use Value: 84 pF capacitance avoids insertion loss in 17 MHz VDSL2 band; 58 V VDRM accommodates ±50 V ringing and longitudinal noise margins. |
| Customer Premises Equipment (CPE) | ISDN BRI Interface Protection |
Use Scenario: Overvoltage hardening of residential VoIP gateways and analog telephone adapters connected to PSTN lines. IC Role / Device Role / Timing Role: Primary surge arrestor on tip/ring inputs, upstream of hybrid circuit and line feed controller. Use Value: 77 V VBO provides margin above 48 V nominal battery and 120 V ringing, ensuring robust triggering without nuisance trips. |
Use Scenario: Protecting ISDN Basic Rate Interface (BRI) S/T reference points in NT1 devices and terminal adapters against EFT and surge events. IC Role / Device Role / Timing Role: Bidirectional protector across the 2B+D bus pair, compliant with ITU-T K.20/K.21 immunity requirements. Use Value: Meets IEC 61000-4-5 (10×700 µs, 75 A) and ITU-T K.20 Level 3, enabling certification-ready BRI port design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protector applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SM2T7.0A (STMicroelectronics) | Unidirectional, 7.0 V VDRM, 100 A (8×20 µs), TO-277 package | Requires dual-device configuration for AC line protection; lower voltage rating limits use to low-voltage data lines only. | Select only for DC-biased or low-voltage (<12 V) signal lines where bidirectionality is not required. |
| P6SMB7.0A (onsemi) | Unidirectional TVS diode, 7.0 V VBR, 100 A (8×20 µs), same SMB package | Lacks latching behavior; clamps but does not crowbar; higher leakage and lower surge endurance than TSPD architecture. | Use where fast response and low clamping voltage are prioritized over sustained surge energy diversion. |
Compared with SM2T7.0A and P6SMB7.0A, the NP0640SCT3G delivers true bidirectional crowbar action with 58 V standoff and 150 A surge capacity - making it uniquely suitable for telecom AC line protection where latching, low clamping voltage, and regulatory compliance (GR-1089, K.20) are mandatory.
Availability
NP0640SCT3G is available at Aetrix Electronics and suitable for central office equipment, DSLAM port protection, and customer premises VoIP gateway designs requiring stable component supply, long-term lifecycle support, and RoHS-compliant surge protection.
Supply support for NP0640SCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and communications markets.
The NP Series TSPDs were developed specifically for telecom infrastructure protection, targeting GR-1089-CORE, ITU-T K.20/K.21, and IEC 61000-4-5 compliance in central office, access network, and CPE applications.
FAQ
What is the primary function of the NP0640SCT3G in a telecom line interface?
The NP0640SCT3G functions as a bidirectional thyristor surge protector (TSPD) that acts as a crowbar during overvoltage events. When line voltage exceeds its 77 V breakover threshold, it switches to low-impedance conduction, diverting surge current away from sensitive downstream components such as codecs or SLICs. It remains latched until current drops below its 150 mA holding current, ensuring complete energy discharge before resetting. This behavior is essential for meeting GR-1089-CORE and ITU-T K.20 immunity requirements in the NP0640SCT3G's target applications.
Does the NP0640SCT3G require a gate drive or external trigger circuit?
No, the NP0640SCT3G is a gateless, voltage-triggered device with no control pin or external bias requirement. It relies solely on intrinsic thyristor physics: conduction initiates when applied voltage across MT1–MT2 exceeds the 77 V breakover voltage (VBO) in either polarity. Its symmetrical structure eliminates polarity sensitivity, and its 58 V peak off-state voltage (VDRM) ensures stable blocking during normal operation. This self-triggering characteristic simplifies design and reduces bill-of-materials count compared to gated protectors or discrete SCR-based solutions.
How does the SMB package of the NP0640SCT3G impact thermal performance in high-surge applications?
The NP0640SCT3G's SMB (DO-214AA) package has a specified thermal resistance of 90 °C/W (Junction-to-Ambient, per JESD51-3 on FR4). In high-surge scenarios, this value dictates safe power derating: for example, a single 150 A/2×10 µs surge dissipates ~600 mJ, resulting in a transient junction temperature rise of ~54 °C - well within the −40 °C to +150 °C operating range. Layout best practices (e.g., 2 oz copper, thermal vias, minimum 3×3 inch pad area) are necessary to achieve the rated RθJA; inadequate copper will elevate temperature and risk thermal runaway during repetitive surges.
Can the NP0640SCT3G be used in DC-powered communication interfaces like RS-485 or CAN?
No, the NP0640SCT3G is not recommended for DC-powered interfaces such as RS-485 or CAN. Its 58 V VDRM and 77 V VBO are optimized for telecom AC line voltages (e.g., ±48 V battery, 90 V ringing), and its 150 mA holding current requires sufficient fault current to sustain conduction - a condition rarely met in low-current DC data buses. Using it in such applications risks failure to latch or unintended disruption of communication. For RS-485/CAN, purpose-built TVS arrays or unidirectional TSPDs with lower VBO (e.g., 15–24 V) and matched holding current are appropriate alternatives to the NP0640SCT3G.
What regulatory standards does the NP0640SCT3G help satisfy in telecom equipment design?
The NP0640SCT3G is explicitly designed to support compliance with multiple telecom-specific immunity standards: GR-1089-CORE (Levels A–C), ITU-T K.20/K.21/K.45, IEC 61000-4-5 (10×700 µs, 10×1000 µs), TIA-968-A, FCC Part 68, EN 60950, and UL 1950. Its 150 A surge rating at 2×10 µs satisfies GR-1089 Level A, while its 75 A rating at 10×700 µs aligns with ITU-T K.20 Level 3. These validated capabilities allow designers to implement single-device protection schemes that reduce validation effort and accelerate time-to-certification for the NP0640SCT3G-equipped system.
NP0640SCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 77V
- Voltage - Off State:
- 58V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- -
- Current - Peak Pulse (10/1000µs):
- 100 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 222pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP0640SCT3G FAQ
1.How can I place an order for NP0640SCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP0640SCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP0640SCT3G reliable?
The price and inventory of NP0640SCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP0640SCT3G is usually 5 days.
3.What payment methods are accepted for NP0640SCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP0640SCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP0640SCT3G?
NP0640SCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP0640SCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP0640SCT3G?
For technical support, including NP0640SCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP0640SCT3G requirements.
6.How does Aetrix verify that NP0640SCT3G is sourced from the original manufacturer or authorized distributors?
All NP0640SCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP0640SCT3G meets industry standards.
7.What is the process for return or replacement of NP0640SCT3G?
All NP0640SCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP0640SCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP0640SCT3G part is unused and in its original packaging.
Return procedure for NP0640SCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NP0640SCT3G Tags

-
TISP4015L1AJR-S
Bourns Inc.

-
TISP4015L1BJR-S
Bourns Inc.

-
SMP100LC-270
STMicroelectronics

-
TISP4240M3BJR-S
Bourns Inc.

-
SMP100LC-35
STMicroelectronics

-
SMP100LC-65
STMicroelectronics

-
SMP100LC-8
STMicroelectronics

-
TISP4P035L1NR-S
Bourns Inc.

-
TISP4350H3BJR-S
Bourns Inc.

-
TISP4011H1BJR-S
Bourns Inc.

-
SMP100LC-400
STMicroelectronics

-
P0300SALRP
Littelfuse Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

