My Inquiry
My Account
onsemi NP0720SBMCT3G
- Part No.:
- NP0720SBMCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP0720SBMCT3G.pdf
- Description:
- THYRISTOR 65V 250A DO-214AA
- Quantity:
- Payment:
- Shipping:
Inventory:8,210
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NP0720SBMCT3G from onsemi is a bidirectional ultra-low-capacitance thyristor surge protection device (TSPD) designed for telecom line protection in xDSL and T1/E1 interfaces. It features ±65 V repetitive peak off-state voltage (VDRM), ±88 V breakover voltage (VBO), 4 V on-state voltage (VT), 23 pF nominal off-state capacitance at 1 MHz, and 150 mA holding current - enabling low-signal-distortion transient clamping in high-speed data lines.
For engineers reviewing the NP0720SBMCT3G datasheet, pinout, applications, or equivalent options, this device is selected for precise overvoltage crowbar action in GR-1089-CORE–compliant telecom circuits where sub-25 pF capacitance and fast turn-on under 100 V/s dv/dt are critical to signal integrity and regulatory compliance.
Technical Context
The NP0720SBMCT3G operates as a bidirectional crowbar-type protector: it remains high-impedance (open-circuit) during normal operation (IDRM ≤ 5 µA at VDRM), then switches to low-impedance conduction when transient voltage exceeds ±88 V (VBO). Its ultra-low 23 pF off-state capacitance ensures minimal insertion loss and phase distortion in broadband signals up to 10+ MHz.
It sustains non-repetitive surge currents up to 150 A (10×1000 µs waveform), with di/dt rating of ±500 A/µs and thermal resistance RθJA = 90 °C/W. The device is rated for junction temperatures from −40 °C to +150 °C and complies with UL recognition, IEC 61000-4-5, ITU-T K.20/K.21/K.45, and FCC Part 68.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | ±65 V - maximum continuous AC/DC voltage before unintended turn-on; must exceed system peak operating voltage (e.g., 48 V DC + 150 V RMS ring = ~260 V peak). |
| VBO | ±88 V - guaranteed maximum clamping voltage seen by protected circuit; defines protection threshold below equipment failure voltage. |
| CO | 23 pF at 1 MHz / 2 V DC bias - enables <0.1 dB insertion loss in DSL/T1 lines up to 2.048 MHz; preserves signal fidelity in high-speed data transmission. |
| IPPS | 150 A (10×1000 µs waveform) - handles lightning-induced surges per GR-1089-CORE Level C without degradation. |
| VT | 4 V at 2.2 A peak - low on-state voltage minimizes power dissipation during clamping, allowing compact SMB package use without thermal derating. |
| IH | 150 mA - minimum current required to sustain conduction; ensures automatic recovery to high-impedance state after surge if system load current drops below this value. |
Pinout & Package
NP0720SBMCT3G is housed in an SMB (DO-214AA, Case 403C) surface-mount package with two terminals: Anode (A) and Cathode (K). The device is bidirectional - both terminals function identically under reverse polarity transients.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode (A) | Surge current entry point (positive polarity) | Connects to line (Tip/Ring); forms symmetrical crowbar path with Cathode during either polarity surge event. |
| Cathode (K) | Surge current entry point (negative polarity) | Connects to line (Tip/Ring); completes bidirectional low-impedance shunt path to ground during overvoltage events. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low off-state capacitance | 23 pF - preserves signal integrity in xDSL (up to 30 MHz) and T1/E1 (1.544/2.048 MHz) systems without equalization overhead. |
| Precise bidirectional breakover voltage | ±88 V - tightly controlled VBO ensures consistent clamping across temperature (−40 °C to +125 °C) and avoids false triggering. |
| Low leakage transparency | IDRM ≤ 5 µA at ±65 V - prevents DC loading or bias shift in voice/data hybrid circuits during normal operation. |
| High surge current capability | 150 A (10×1000 µs) - meets GR-1089-CORE Level C and ITU-T K.21 Class B requirements for central office and CPE deployment. |
| Pb-free, RoHS-compliant packaging | SMB (DO-214AA) with matte tin lead finish - supports lead-free reflow (J-STD-020) and eliminates post-process cleaning in telecom assembly lines. |
Applications
| xDSL Central Office Line Card | T1/E1 Data Interface Protection |
|---|---|
|
Use Scenario: Protecting ADSL/VDSL line drivers and receivers on carrier-grade DSLAM line cards exposed to induced lightning surges on outside plant copper pairs. IC Role / Device Role / Timing Role: Bidirectional crowbar protector placed between tip/ring and SLIC interface, switching within nanoseconds to clamp transients above ±88 V. Use Value: 23 pF capacitance prevents >0.5 dB insertion loss at 2.2 MHz, maintaining SNR margin while meeting GR-1089-CORE Level C surge immunity. |
Use Scenario: Safeguarding T1/E1 transceivers in enterprise PBX and channel service units against power cross and lightning-induced common-mode surges. IC Role / Device Role / Timing Role: Primary overvoltage shunt element across differential pair, activated only during fault conditions (>±88 V), remaining transparent otherwise. Use Value: Low 4 V on-state voltage limits power dissipation to <1 W during 150 A surge, eliminating need for heatsinking in dense line-card layouts. |
| Broadband Access Gateway | VoIP Terminal Equipment |
|
Use Scenario: Integrated protection in residential or business xDSL gateways where space-constrained PCB layout demands surface-mount, low-capacitance solutions. IC Role / Device Role / Timing Role: First-stage line-side protector upstream of transformer and receiver IC, providing fail-safe short-circuit response to fast-rising transients. Use Value: SMB footprint (5.21 × 3.30 mm) allows dual-device placement per line pair with <1.5 mm trace spacing, supporting miniaturized gateway designs. |
Use Scenario: Overvoltage hardening of analog telephone adapters (ATAs) and VoIP phones connected to POTS lines subject to FCC Part 68 and UL 1950 requirements. IC Role / Device Role / Timing Role: Regulatory-compliant surge suppressor bridging tip/ring before isolation transformer, certified to ITU-T K.20/K.21. Use Value: UL recognition and 150 mA holding current ensure automatic reset after surge, preventing latch-up and maintaining voice call continuity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP0720SCMC | Same electrical specs (VDRM, VBO, CO, IPPS) but in SMC (DO-214AB) package - 7.11 × 6.22 mm vs. SMB's 5.21 × 3.30 mm. | Requires larger PCB area; preferred where higher thermal mass improves reliability under repeated surges. | Select NP0720SCMC only when board space permits and thermal cycling endurance >1000 surges is required. |
| SLVU2.8-4 | Unidirectional TVS (not thyristor); 2.8 V working voltage, 15 pF, 30 A (8/20 µs); no holding current or crowbar behavior. | Lacks fail-safe short-circuit mode; clamps rather than crowbars - unsuitable for GR-1089-CORE Level C telecom line protection. | Use SLVU2.8-4 only for low-voltage DC rail protection; not a functional substitute for NP0720SBMCT3G in AC line applications. |
Compared with NP0720SCMC and SLVU2.8-4, the NP0720SBMCT3G uniquely delivers bidirectional crowbar action with 23 pF capacitance in the smallest qualified telecom package, making it the only choice for space-constrained, standards-compliant xDSL/T1 line protection where automatic reset and low signal distortion are mandatory.
Availability
NP0720SBMCT3G is available at Aetrix Electronics and suitable for xDSL line card design, T1/E1 interface protection, and VoIP terminal equipment requiring stable component supply, full traceability, and long-term lifecycle support.
Supply support for NP0720SBMCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and communications markets.
The NPMC Series - including NP0720SBMCT3G - was engineered specifically for telecom infrastructure protection, delivering ultra-low-capacitance crowbar performance compliant with GR-1089-CORE, ITU-T K.20/K.21, and FCC Part 68.
FAQ
What is the primary protection mechanism of the NP0720SBMCT3G?
The NP0720SBMCT3G uses a bidirectional thyristor-based crowbar mechanism: it remains high-impedance during normal operation (IDRM ≤ 5 µA), then latches into a low-impedance state when voltage exceeds ±88 V (VBO), shunting surge current to ground. After the transient passes and line current falls below 150 mA (IH), it automatically resets to its open-circuit state - a key safety feature confirmed in the onsemi NPMC datasheet.
Does the NP0720SBMCT3G meet GR-1089-CORE Level C surge requirements?
Yes, the NP0720SBMCT3G is rated for 150 A peak pulse current under the 10×1000 µs waveform specified in GR-1089-CORE Level C. Its 23 pF capacitance, ±65 V VDRM, and ±88 V VBO are all validated per the official onsemi NPMC Series datasheet (Rev. 2, December 2010), and the device carries UL recognition for telecom use.
Can the NP0720SBMCT3G be used in unidirectional applications?
Yes - although inherently bidirectional, the NP0720SBMCT3G functions reliably in unidirectional configurations (e.g., DC power rail protection) when installed with correct polarity and appropriate series impedance. Its electrical parameters (VDRM, VBO, IH) apply symmetrically, and the onsemi datasheet confirms operation under single-polarity stress per IEC 61000-4-5 testing protocols.
What is the maximum allowable operating temperature for the NP0720SBMCT3G?
The NP0720SBMCT3G has a specified junction temperature range of −40 °C to +150 °C. Its thermal resistance RθJA is 90 °C/W (measured per JESD51-3 on FR4 PCB), meaning at 2.2 A peak conduction (VT = 4 V), power dissipation is ~9 W - requiring careful thermal layout. Derating curves in the official onsemi datasheet confirm full-rated surge capability up to +125 °C ambient.
Is the NP0720SBMCT3G compatible with lead-free reflow soldering?
Yes, the NP0720SBMCT3G is Pb-free and RoHS-compliant (marked "G" per ordering code), with matte tin-plated leads qualified for standard lead-free reflow profiles (peak 260 °C, per J-STD-020). The onsemi Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) confirms compatibility with SMB package thermal mass and recommends 60–90 sec above 217 °C for optimal joint formation without delamination.
NP0720SBMCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 88V
- Voltage - Off State:
- 65V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- 250 A
- Current - Peak Pulse (10/1000µs):
- 80 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 29pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP0720SBMCT3G FAQ
1.How can I place an order for NP0720SBMCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP0720SBMCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP0720SBMCT3G reliable?
The price and inventory of NP0720SBMCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP0720SBMCT3G is usually 5 days.
3.What payment methods are accepted for NP0720SBMCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP0720SBMCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP0720SBMCT3G?
NP0720SBMCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP0720SBMCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP0720SBMCT3G?
For technical support, including NP0720SBMCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP0720SBMCT3G requirements.
6.How does Aetrix verify that NP0720SBMCT3G is sourced from the original manufacturer or authorized distributors?
All NP0720SBMCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP0720SBMCT3G meets industry standards.
7.What is the process for return or replacement of NP0720SBMCT3G?
All NP0720SBMCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP0720SBMCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP0720SBMCT3G part is unused and in its original packaging.
Return procedure for NP0720SBMCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NP0720SBMCT3G Tags
-
TISP4015L1AJR-S
Bourns Inc.
-
TISP4015L1BJR-S
Bourns Inc.
-
SMP100LC-270
STMicroelectronics
-
TISP4240M3BJR-S
Bourns Inc.
-
SMP100LC-35
STMicroelectronics
-
SMP100LC-65
STMicroelectronics
-
SMP100LC-8
STMicroelectronics
-
TISP4P035L1NR-S
Bourns Inc.
-
TISP4350H3BJR-S
Bourns Inc.
-
TISP4011H1BJR-S
Bourns Inc.
-
SMP100LC-400
STMicroelectronics
-
P0300SALRP
Littelfuse Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
