onsemi NP1100SCT3G
- Part No.:
- NP1100SCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP1100SCT3G.pdf
- Description:
- THYRISTOR 90V 100A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:2,535
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NP1100SCT3G from onsemi is a bidirectional thyristor surge protector (TSPD) designed for overvoltage protection in telecom line interfaces. It features 90 V peak off-state voltage (VDRM), 130 V breakover voltage (VBO), 4 V on-state voltage (VT), 150 mA holding current (IH), and supports 10×1000 µs surge currents up to 50 A(pk), making it suitable for GR-1089-CORE and ITU-T K.20/K.21 compliant central office and access equipment.
For engineers reviewing the NP1100SCT3G datasheet, pinout, applications, or equivalent options, this page delivers verified electrical parameters, SMB package dimensions, bidirectional crowbar behavior, surge waveform compliance data, and direct alternatives for telecom surge protection design.
Technical Context
The NP1100SCT3G operates as a voltage-triggered bidirectional crowbar device: it remains high-impedance below VDRM (90 V), switches to low-impedance conduction at VBO (130 V ±5%), and latches until current falls below IH (150 mA). Its 4.0 V on-state voltage limits clamping loss during surge events.
It meets critical telecom surge standards including GR-1089-CORE (2×10 µs, 10×1000 µs), TIA-968-A (10×160 µs), and ITU-T K.20/21 (10×700 µs), with peak surge current ratings of 50 A(pk) at 10×1000 µs and 75 A(pk) at 10×360 µs under specified test conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | 90 V - Maximum continuous off-state voltage before triggering in either polarity |
| VBO | 130 V - Breakover voltage threshold where device switches to low-impedance conduction |
| VT | 4.0 V - On-state voltage drop at 1.0 A(pk), defining power dissipation during clamping |
| IH | 150 mA - Minimum current required to maintain conduction after triggering |
| IPPS (10×1000 µs) | 50 A(pk) - Non-repetitive surge current capability per GR-1089-CORE compliance |
| CO | 58 pF - Typical capacitance at 1 MHz, 1 Vrms, 2 Vdc bias, minimizing signal distortion |
| dV/dt (critical) | 5.0 kV/s - Minimum rate of voltage rise that ensures reliable triggering without false turn-on |
Pinout & Package
NP1100SCT3G is housed in an SMB (DO-214AA) surface-mount package (Case 403C), measuring 4.57 mm × 3.81 mm × 2.11 mm (L × W × H), with gull-wing leads optimized for automated assembly and thermal dissipation on FR4 PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MT1 | Main Terminal 1 | Anode for positive polarity conduction; cathode for negative polarity conduction - bidirectional main current path |
| MT2 | Main Terminal 2 | Cathode for positive polarity conduction; anode for negative polarity conduction - completes bidirectional current loop |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional crowbar action | Enables single-device protection of AC-coupled telecom lines without polarity-sensitive placement |
| GR-1089-CORE & ITU-T K.20/21 compliance | Validated surge performance across 2×10 µs to 10×1000 µs waveforms eliminates need for external test validation |
| Low 58 pF capacitance | Minimizes insertion loss and signal integrity impact on high-speed DSL/VDSL/POTS line interfaces |
| Pb-free, RoHS-compliant SMB package | Supports lead-free reflow soldering (JEDEC J-STD-020) and industrial environmental compliance requirements |
| 150°C maximum junction temperature | Ensures reliable operation in sealed central office cabinets and outdoor access nodes with limited airflow |
Applications
| DSL Line Interface Protection | Central Office Subscriber Line Card |
|---|---|
Use Scenario: Protects ADSL2+/VDSL2 transceivers from lightning-induced surges on twisted-pair copper loops. IC Role / Device Role / Timing Role: Bidirectional crowbar device placed between line transformer secondary and codec IC input. Use Value: Clamps transient energy above 130 V while maintaining <58 pF loading to preserve signal bandwidth up to 30 MHz. |
Use Scenario: Integrated into multi-channel SLIC-based line cards handling 24–48 subscriber lines in Class 5 switches. IC Role / Device Role / Timing Role: Primary overvoltage protector on each analog line interface, coordinated with gas discharge tubes (GDTs) for staged protection. Use Value: Withstands 50 A(pk) 10×1000 µs surges per GR-1089-CORE, enabling single-device compliance without parallel devices. |
| IP-PBX Analog Trunk Interface | Remote Terminal Cabinet Protection |
Use Scenario: Shields FXO/FXS ports of enterprise IP-PBX systems connected to PSTN lines. IC Role / Device Role / Timing Role: First-stage solid-state protector upstream of GDTs and PTCs in hybrid protection circuits. Use Value: Fast response (<100 ns) to overvoltage events prevents damage to sensitive VoIP controller ICs and isolation transformers. |
Use Scenario: Installed in outdoor remote terminals serving fiber-to-the-curb (FTTC) distribution points. IC Role / Device Role / Timing Role: Final-stage protector after primary GDT suppression, handling residual fast-rising transients. Use Value: 90 V VDRM allows safe operation under normal -48 V DC line bias while blocking induced noise below trigger threshold. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protector applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP1100SBT3G | Same electrical specs and SMB package; differs only in marking code (110B vs. 110C) and surge rating tier B (75 A at 10×360 µs vs. 50 A at 10×1000 µs) | Preferred where higher short-duration surge immunity (e.g., TIA-968-A 10×160 µs) is prioritized over long-tail energy handling | Select NP1100SBT3G when system-level testing shows dominant threat is fast-rising surges rather than long-tail lightning currents |
| SLVU2.8-4 | Unidirectional TVS diode array (2.8 V clamp), not a thyristor; lower VBR, no latching, 30 pF typical capacitance | Suitable only for low-voltage data lines (e.g., Ethernet PHY, USB), not for -48 V telecom line protection | Use SLVU2.8-4 only for sub-5 V signal rails; NP1100SCT3G remains required for primary analog line protection |
Compared with NP1100SBT3G and SLVU2.8-4, the NP1100SCT3G provides uniquely balanced long-tail surge handling (50 A at 10×1000 µs) and telecom-grade voltage standoff (90 V VDRM), making it irreplaceable for GR-1089-CORE-compliant central office line card designs.
Availability
NP1100SCT3G is available at Aetrix Electronics and suitable for DSL line interface protection, central office subscriber line cards, and IP-PBX analog trunk interfaces requiring stable component supply, full RoHS compliance, and documented GR-1089-CORE surge performance.
Supply support for NP1100SCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and communications markets.
The NP Series thyristor surge protectors were developed specifically for telecom infrastructure applications requiring robust, bidirectional, high-voltage overvoltage protection with standardized surge compliance and surface-mount reliability.
FAQ
What is the peak off-state voltage rating for NP1100SCT3G?
The NP1100SCT3G has a peak off-state voltage (VDRM) rating of 90 V in both polarities, meaning it blocks up to 90 V continuously without triggering. This value is confirmed in the Electrical Characteristics table on page 2 of the official datasheet and defines its safe operating range on -48 V telecom lines with normal DC bias and superimposed AC signals.
Does NP1100SCT3G meet GR-1089-CORE compliance?
Yes, the NP1100SCT3G is explicitly rated for GR-1089-CORE compliance, supporting 2×10 µs (150 A), 10×360 µs (75 A), and 10×1000 µs (50 A) surge waveforms as listed in the Surge Data Ratings table on page 2 of the datasheet. These values are measured per standard test methods and apply directly to the NP1100SCT3G device.
What package type does NP1100SCT3G use?
The NP1100SCT3G uses the SMB (DO-214AA) surface-mount package, designated Case 403C in onsemi documentation. Its mechanical dimensions - 4.57 mm × 3.81 mm × 2.11 mm - and gull-wing lead configuration are fully detailed in the Package Dimensions drawing on page 5 of the datasheet.
How does NP1100SCT3G differ from unidirectional TVS diodes like SLVU2.8-4?
Unlike unidirectional TVS diodes, the NP1100SCT3G is a bidirectional thyristor that latches into low-impedance conduction until current drops below 150 mA. It handles much higher surge energy (50 A at 10×1000 µs) and operates at telecom line voltages (90 V VDRM), whereas SLVU2.8-4 clamps at 2.8 V and is unsuitable for primary analog line protection.
What is the on-state voltage of NP1100SCT3G during surge conduction?
The NP1100SCT3G exhibits a maximum on-state voltage (VT) of 4.0 V when conducting 1.0 A(pk) under pulsed conditions (300 µs pulse width, 2% duty cycle), as specified in the Electrical Characteristics table. This low clamping voltage minimizes power dissipation and thermal stress during surge events.
NP1100SCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 130V
- Voltage - Off State:
- 90V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- -
- Current - Peak Pulse (10/1000µs):
- 100 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 154pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP1100SCT3G FAQ
1.How can I place an order for NP1100SCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP1100SCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP1100SCT3G reliable?
The price and inventory of NP1100SCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP1100SCT3G is usually 5 days.
3.What payment methods are accepted for NP1100SCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP1100SCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP1100SCT3G?
NP1100SCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP1100SCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP1100SCT3G?
For technical support, including NP1100SCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP1100SCT3G requirements.
6.How does Aetrix verify that NP1100SCT3G is sourced from the original manufacturer or authorized distributors?
All NP1100SCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP1100SCT3G meets industry standards.
7.What is the process for return or replacement of NP1100SCT3G?
All NP1100SCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP1100SCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP1100SCT3G part is unused and in its original packaging.
Return procedure for NP1100SCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NP1100SCT3G Tags

-
TISP4015L1AJR-S
Bourns Inc.

-
TISP4015L1BJR-S
Bourns Inc.

-
SMP100LC-270
STMicroelectronics

-
TISP4240M3BJR-S
Bourns Inc.

-
SMP100LC-35
STMicroelectronics

-
SMP100LC-65
STMicroelectronics

-
SMP100LC-8
STMicroelectronics

-
TISP4P035L1NR-S
Bourns Inc.

-
TISP4350H3BJR-S
Bourns Inc.

-
TISP4011H1BJR-S
Bourns Inc.

-
SMP100LC-400
STMicroelectronics

-
P0300SALRP
Littelfuse Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

