onsemi NP1300SAT3G
- Part No.:
- NP1300SAT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP1300SAT3G.pdf
- Description:
- THYRISTOR 120V 50A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:2,567
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Product details
Overview
NP1300SAT3G from onsemi is a bidirectional thyristor surge protector (TSPD) designed for overvoltage clamping in telecom line interfaces. It features 120 V peak off-state voltage (VDRM), 160 V breakover voltage (VBO), 4.0 V on-state voltage (VT), 150 mA holding current (IH), and supports up to 500 A(pk) 10×1000 µs surge current per GR-1089-CORE. It protects central office, access, and customer premises equipment.
For engineers reviewing the NP1300SAT3G datasheet, pinout, applications, or equivalent options, key selection criteria include bidirectional crowbar action, SMB package compatibility, 120 V/160 V voltage ratings, compliance with ITU-T K.20/K.21/GR-1089-CORE, and thermal resistance of 90 °C/W.
Technical Context
The NP1300SAT3G operates as a voltage-triggered bidirectional crowbar device: it remains high-impedance below VDRM (120 V), triggers at ±160 V (VBO), latches on with ≥2.2 A (IT) and holds conduction until current falls below IH (150 mA). Its dv/dt rating is 5.0 kV/s, ensuring immunity to false triggering under fast transients.
It delivers robust surge handling: 50 A(pk) @ 10×1000 µs, 75 A(pk) @ 10×360 µs, and 150 A(pk) @ 2×10 µs per GR-1089-CORE - all with ≤4.0 V clamping (VT) during conduction. Capacitance is 46 pF (typ) at 1 MHz, minimizing signal distortion in voice/data lines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | 120 V - Maximum continuous reverse/forward blocking voltage before conduction |
| VBO | 160 V - Symmetrical breakover voltage threshold for both polarities |
| VT | 4.0 V - Clamped voltage across device during surge conduction at 1.0 A |
| IH | 150 mA - Minimum current required to sustain conduction after triggering |
| IPPS7 | 50 A(pk) - Non-repetitive surge current capability for 10×1000 µs waveform |
| CO | 46 pF - Signal-line capacitance at 1 MHz, critical for DSL/VoIP bandwidth preservation |
| dv/dt | 5.0 kV/s - Minimum rate of voltage rise tolerated without spurious turn-on |
Pinout & Package
NP1300SAT3G is housed in an SMB (DO-214AA, Case 403C) surface-mount package with two terminals: MT1 and MT2. The device is symmetrical and bidirectional; either terminal may serve as anode or cathode depending on transient polarity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MT1 | Main Terminal 1 | Current-carrying electrode; interchangeable with MT2 due to bidirectional symmetry |
| MT2 | Main Terminal 2 | Current-carrying electrode; forms conduction path with MT1 during crowbar event |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional crowbar protection | Single-device replacement for back-to-back SCRs; eliminates layout asymmetry and matching concerns |
| GR-1089-CORE & ITU-T K.20/K.21 compliance | Validated for telecom infrastructure use including central office and DSLAM line cards |
| Low 46 pF capacitance | Preserves >10 MHz signal integrity in ADSL2+/VDSL2 lines without equalization penalty |
| Pb-free SMB package (JEDEC DO-214AA) | Enables automated reflow assembly; footprint compatible with industry-standard 2-pin SMD pads |
| −40°C to +150°C operating range | Supports deployment in uncontrolled environments such as outdoor cabinets and remote terminals |
Applications
| DSL Line Card Protection | VoIP Gateway Interface |
|---|---|
|
Use Scenario: Protects copper-pair interfaces in DSLAM line cards against lightning-induced surges and AC power cross. IC Role / Device Role / Timing Role: Bidirectional crowbar that clamps transients above 160 V and diverts >50 A surge energy to ground. Use Value: Prevents damage to line driver ICs and transformer windings while maintaining <46 pF signal path loading. |
Use Scenario: Shields analog telephone interface (FXS/FXO) circuits in VoIP gateways from induced surges on POTS lines. IC Role / Device Role / Timing Role: Voltage-triggered latch that conducts only during overvoltage events, remaining transparent during normal operation. Use Value: Enables single-device protection without DC bias networks or polarity-sensitive placement. |
| Central Office SLIC Protection | Customer Premises Equipment (CPE) |
|
Use Scenario: Installed upstream of SLIC (Subscriber Line Interface Circuit) ICs to absorb longitudinal surges per GR-1089-CORE Level 3. IC Role / Device Role / Timing Role: High-energy crowbar with 90 °C/W thermal resistance, enabling sustained conduction without thermal runaway. Use Value: Eliminates need for series impedance or gas discharge tubes, reducing BOM count and board space. |
Use Scenario: Integrated into residential gateways, modems, and IP phones to meet FCC Part 68 and UL 1950 surge requirements. IC Role / Device Role / Timing Role: RoHS-compliant, SMB-packaged protector rated for 120 V working voltage and 160 V trigger. Use Value: Simplifies certification by providing pre-validated surge performance across multiple regulatory waveforms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protector applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP1300SBT3G | Same electrical specs and SMB package; differs only in marking code (130B vs. 130A) and surge rating tier (B-tier: 10×1000 µs = 80 A vs. A-tier = 50 A) | Rated for higher 10×1000 µs surge (80 A vs. 50 A); intended for more demanding central office deployments | Select NP1300SBT3G when system-level testing requires margin beyond GR-1089-CORE Level 2 (50 A) and approaches Level 3 (80 A) |
| SM1300A | 130 V VDRM, 165 V VBO, 4.5 V VT, 40 pF CO; SMB package; Littelfuse part with tighter VBO tolerance but higher on-state voltage | Lower capacitance improves high-frequency response but higher VT increases power dissipation during clamping | Choose SM1300A where signal bandwidth exceeds 20 MHz and thermal budget allows 0.5 V higher clamping drop |
Compared with NP1300SBT3G and SM1300A, the NP1300SAT3G offers the lowest VT (4.0 V) among SMB TSPDs at this voltage class, reducing joule heating during surge events - critical for densely packed line cards with limited airflow.
Availability
NP1300SAT3G is available at Aetrix Electronics and suitable for DSL line cards, VoIP gateways, and central office SLIC protection requiring stable component supply, RoHS-compliant packaging, and GR-1089-CORE validation.
Supply support for NP1300SAT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and communications markets.
The NP Series TSPDs were developed specifically for telecom infrastructure protection, targeting compliance with GR-1089-CORE, ITU-T K.20/K.21, and FCC Part 68 - with emphasis on bidirectional symmetry, low capacitance, and high surge robustness in compact SMB packages.
FAQ
What is the maximum surge current rating for NP1300SAT3G under the 10×1000 µs waveform?
The NP1300SAT3G is rated for 50 A(pk) under the 10×1000 µs double-exponential waveform per GR-1089-CORE Level 2. This value is specified in the "SURGE RATINGS" table on page 3 of the official datasheet (Rev. 5, May 2008), and reflects non-repetitive capability with adequate cooling between pulses. The NP1300SAT3G must not be subjected to repeated surges exceeding this limit without thermal recovery time.
Is NP1300SAT3G pin-compatible with other NP Series devices in the SMB package?
Yes - all NP Series TSPDs in the SMB package, including NP1300SAT3G, share identical pinout (MT1 and MT2), mechanical dimensions, and solder footprint per JEDEC DO-214AA. The marking "130A" identifies the NP1300SAT3G variant, but electrical differences (e.g., VDRM, VBO, surge rating) require verification per design requirements; physical replacement is mechanically feasible but functionally conditional.
Does NP1300SAT3G require a gate trigger or external control circuitry?
No - the NP1300SAT3G is a passive, voltage-triggered thyristor device with no gate terminal. It operates autonomously: conduction initiates when voltage across MT1–MT2 exceeds ±160 V (VBO), latches on above 2.2 A (IT), and sustains conduction until current drops below 150 mA (IH). No bias, timing, or control signals are needed for NP1300SAT3G operation.
What is the thermal resistance (RθJA) of NP1300SAT3G, and how does it affect layout?
The NP1300SAT3G has a junction-to-ambient thermal resistance of 90 °C/W under JEDEC JESD51-3 conditions (FR4 PCB, 3″×4.5″, 2 oz copper, 3×3 inch fan-out pattern). This means each watt of surge power dissipated during clamping raises junction temperature by ~90 °C - so layouts must provide adequate copper area and avoid thermal isolation to prevent exceeding the +150 °C max operating temperature.
Can NP1300SAT3G be used in DC power line protection applications?
No - the NP1300SAT3G is optimized for AC-coupled telecom line protection (e.g., POTS, DSL, ISDN) and relies on natural current zero-crossings to reset after conduction. In DC applications, once triggered, it remains latched until external current interruption occurs. For DC bus protection, discrete TVS diodes or GDT-based solutions with active reset are recommended instead of NP1300SAT3G.
NP1300SAT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 160V
- Voltage - Off State:
- 120V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- -
- Current - Peak Pulse (10/1000µs):
- 50 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 46pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP1300SAT3G FAQ
1.How can I place an order for NP1300SAT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP1300SAT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP1300SAT3G reliable?
The price and inventory of NP1300SAT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP1300SAT3G is usually 5 days.
3.What payment methods are accepted for NP1300SAT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP1300SAT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP1300SAT3G?
NP1300SAT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP1300SAT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP1300SAT3G?
For technical support, including NP1300SAT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP1300SAT3G requirements.
6.How does Aetrix verify that NP1300SAT3G is sourced from the original manufacturer or authorized distributors?
All NP1300SAT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP1300SAT3G meets industry standards.
7.What is the process for return or replacement of NP1300SAT3G?
All NP1300SAT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP1300SAT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP1300SAT3G part is unused and in its original packaging.
Return procedure for NP1300SAT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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