onsemi NP1300SBMCT3G
- Part No.:
- NP1300SBMCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP1300SBMCT3G.pdf
- Description:
- THYRISTOR 120V 250A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:8,252
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Product details
Overview
NP1300SBMCT3G from onsemi is a bidirectional ultra-low-capacitance thyristor surge protection device (TSPD) designed for telecom line protection in xDSL and T1/E1 interfaces. It features ±120 V repetitive peak off-state voltage (VDRM), ±160 V breakover voltage (V(BO)), 23 pF nominal off-state capacitance at 1.0 MHz, 4 V on-state voltage at 2.2 A peak, and 150 mA holding current - enabling low-signal-distortion transient clamping in high-speed data lines.
For engineers reviewing the NP1300SBMCT3G datasheet, pinout, applications, or equivalent options, this device is selected for precise overvoltage threshold control, minimal capacitive loading on differential pairs, compliance with GR-1089-CORE and ITU-T K.20/K.21, and robust 150 A non-repetitive surge current handling per 10×1000 µs waveform.
Technical Context
The NP1300SBMCT3G operates as a crowbar-type protector: it remains high-impedance (open-circuit) during normal operation (IDRM ≤ 5 µA at VDRM), then switches to low-impedance (short-circuit) when transient voltage exceeds V(BO), shunting surge current to ground. Its bidirectional symmetry supports AC-coupled telecom lines without polarity constraints.
Thermal design relies on SMB package's 90 °C/W junction-to-ambient resistance; electrical behavior is defined by tightly specified VDRM/V(BO) margin (±120 V / ±160 V), low VT (4 V), and stable Co (23 pF across A/B/C ratings), ensuring predictable clamping and minimal signal integrity impact up to 10+ MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | ±120 V - maximum continuous line voltage the device blocks without triggering, ensuring transparency during 48 V DC + 150 V RMS ring voltage (212 V peak) operation |
| V(BO) | ±160 V - guaranteed maximum clamping voltage seen by protected circuit, set below SLIC or relay failure thresholds |
| Co | 23 pF at 1.0 MHz, 1.0 Vrms, 2 Vdc bias - ultra-low capacitance preserves signal integrity in ADSL/T1 broadband channels |
| VT | 4 V at 2.2 A pk, 300 µs pulse - low on-state voltage enables efficient 150 A surge dissipation in compact SMB footprint |
| IH | 150 mA - minimum current required to sustain conduction; must exceed system fault-hold current to auto-reset post-surge |
| IPPS7 | 50 A pk (10×1000 µs waveform) - non-repetitive surge rating compliant with GR-1089-CORE Category C test levels |
| TJ Range | −40 °C to +150 °C - extended junction temperature support for industrial telecom equipment operating in uncontrolled environments |
Pinout & Package
The NP1300SBMCT3G is housed in an SMB (DO-214AA, Case 403C) surface-mount package with two terminals: Anode and Cathode arranged in a symmetrical bidirectional configuration. The package measures 4.06–4.57 mm (A) × 3.30–3.81 mm (B) × 1.90–2.41 mm (C) and is RoHS-compliant and lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode | Surge current entry point (bidirectional) | Accepts transient energy from either polarity; connects to line side of protected interface |
| Cathode | Surge current exit point (bidirectional) | Routes clamped current to ground reference; symmetric with Anode for AC line protection |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low off-state capacitance | 23 pF ensures <0.5% signal attenuation at 2.2 MHz (ADSL2+ upstream band), preserving bit error rate |
| Precise bidirectional breakover voltage | ±160 V tolerance window (±120 V VDRM → ±160 V V(BO)) enables deterministic protection margin vs. equipment failure thresholds |
| Low leakage current | ≤5 µA at ±120 V allows transparent operation in always-on telecom line circuits without DC loading |
| High surge current capability | 50 A peak (10×1000 µs) meets GR-1089-CORE Category C requirements for central office equipment |
| Pb-free SMB packaging | RoHS-compliant DO-214AA footprint supports automated reflow assembly and IPC-J-STD-020 moisture sensitivity level 1 handling |
Applications
| ADSL Central Office Line Card | T1/E1 Data Interface |
|---|---|
Use Scenario: Protecting DSLAM line cards from lightning-induced surges on twisted-pair subscriber loops carrying up to 2.2 MHz ADSL2+ signals. IC Role / Device Role / Timing Role: Bidirectional crowbar protector placed across tip/ring pair before line driver/receiver ICs. Use Value: 23 pF capacitance prevents high-frequency roll-off; ±160 V V(BO) clamps transients below SLIC IC breakdown (typically ±170 V), avoiding latch-up. | Use Scenario: Safeguarding T1/E1 framer and transceiver ICs in telecom access equipment exposed to induced surges on 1.544/2.048 Mbps digital lines. IC Role / Device Role / Timing Role: Primary overvoltage clamp on balanced differential transmit/receive paths. Use Value: Symmetric ±120 V VDRM blocks normal 100 Vpk T1 idle voltage; 50 A IPPS7 rating handles worst-case GR-1089 10×1000 µs surges without degradation. |
| Broadband Customer Premises Equipment | VoIP Gateway Protection |
Use Scenario: Integrated surge protection in residential DSL modems and gateways where PCB space and signal fidelity are constrained. IC Role / Device Role / Timing Role: Front-end transient suppressor on RJ-11 telephone line inputs prior to isolation transformers. Use Value: SMB package fits dense layouts; low VT (4 V) minimizes power dissipation during multi-pulse events, preventing thermal runaway. | Use Scenario: Protecting analog front-end (AFE) and codec ICs in VoIP adapters connected to PSTN lines subject to FCC Part 68 and UL 1950 requirements. IC Role / Device Role / Timing Role: Regulatory-compliant overvoltage guard on FXS/FXO interfaces. Use Value: Certified compliance with ITU-T K.20/K.21 and EN 60950 ensures acceptance in global carrier deployments without additional system-level testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP1300SCMC | Same electrical specs (VDRM, V(BO), Co, VT), but in SMC (DO-214AB) package - 5.29 mm × 6.22 mm vs. SMB's 4.57 mm × 3.81 mm | Requires larger PCB footprint; higher thermal resistance (60 °C/W vs. 90 °C/W) reduces surge duty cycle margin | Select NP1300SCMC only if board layout accommodates larger SMC and higher peak power dissipation is needed |
| SM1300A | Monolithic dual-thyristor array with matched ±130 V VDRM; 35 pF Co - 52% higher capacitance than NP1300SBMCT3G | Designed for differential pair protection (tip/ring) in single package; not a direct replacement for single-line use | Choose SM1300A when protecting both conductors simultaneously; avoid for single-ended or space-constrained designs |
Compared with NP1300SCMC and SM1300A, the NP1300SBMCT3G delivers optimal balance of ultra-low 23 pF capacitance, compact SMB footprint, and certified GR-1089 compliance - making it preferred for high-density xDSL line cards where signal integrity and board area are critical.
Availability
NP1300SBMCT3G is available at Aetrix Electronics and suitable for xDSL central office systems, T1/E1 telecom infrastructure, and VoIP gateway designs requiring stable component supply, long-term lifecycle assurance, and full regulatory documentation traceability.
Supply support for NP1300SBMCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensor, and logic solutions for automotive, industrial, and communications markets.
The NPMC Series, including NP1300SBMCT3G, was engineered specifically for telecom line protection - delivering ultra-low capacitance, precise bidirectional clamping, and GR-1089/ITU-T compliance in surface-mount packages.
FAQ
What is the primary function of the NP1300SBMCT3G in a telecom circuit?
The NP1300SBMCT3G functions as a bidirectional thyristor surge protection device (TSPD) that remains transparent (high-impedance) during normal operation but triggers into a low-impedance "crowbar" state when line voltage exceeds ±160 V, diverting surge current to ground. In the NP1300SBMCT3G, this action protects downstream SLICs, codecs, and framer ICs in xDSL and T1/E1 equipment from lightning-induced transients while adding only 23 pF capacitance.
Does the NP1300SBMCT3G meet GR-1089-CORE and ITU-T K.20/K.21 standards?
Yes, the NP1300SBMCT3G is explicitly qualified to GR-1089-CORE (Category C, 10×1000 µs, 50 A), ITU-T K.20/K.21 (10×700 µs, 75 A), and other key telecom standards including FCC Part 68 and EN 60950. These certifications are documented in onsemi's NPMC Series datasheet (Order Number NP0640SAMC/D), confirming the NP1300SBMCT3G's suitability for carrier-grade central office and customer premises equipment.
What is the significance of the "B" in NP1300SBMCT3G?
The "B" in NP1300SBMCT3G denotes the specific variant within the NPMC Series rated for ±120 V VDRM and ±160 V V(BO); it distinguishes this part from other members like NP1300SCMC (same ratings, SMC package) or NP1300SxMCT3G variants with different voltage grades. The full marking "NP1300SBMCT3G" confirms RoHS-compliant SMB packaging (T3G suffix), with "B" indicating the exact electrical bin and performance group validated in the original datasheet.
Can the NP1300SBMCT3G be used in DC-powered telecom interfaces?
Yes, the NP1300SBMCT3G supports DC-biased telecom interfaces such as 48 V DC-powered xDSL lines. Its ±120 V VDRM exceeds the combined peak of 48 V DC plus 150 V RMS ringing voltage (212 V), and its ≤5 µA IDRM at VDRM ensures negligible leakage under steady-state conditions. The NP1300SBMCT3G's bidirectional symmetry also accommodates AC-coupled voice channels without polarity concerns.
How does the NP1300SBMCT3G's 23 pF capacitance impact high-speed data transmission?
The NP1300SBMCT3G's 23 pF off-state capacitance introduces minimal impedance mismatch on differential telecom lines: at 2.2 MHz (ADSL2+ upstream limit), capacitive reactance is ~3.1 kΩ, causing <0.5% signal attenuation and preserving SNR and bit error rate. This value is confirmed in the datasheet's Figure 4 (Capacitance vs. Off-State Voltage) and is significantly lower than legacy TVS diodes (>100 pF), making the NP1300SBMCT3G suitable for broadband applications where signal fidelity is critical.
NP1300SBMCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 160V
- Voltage - Off State:
- 120V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- 250 A
- Current - Peak Pulse (10/1000µs):
- 80 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 29pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP1300SBMCT3G FAQ
1.How can I place an order for NP1300SBMCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP1300SBMCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP1300SBMCT3G reliable?
The price and inventory of NP1300SBMCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP1300SBMCT3G is usually 5 days.
3.What payment methods are accepted for NP1300SBMCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP1300SBMCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP1300SBMCT3G?
NP1300SBMCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP1300SBMCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP1300SBMCT3G?
For technical support, including NP1300SBMCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP1300SBMCT3G requirements.
6.How does Aetrix verify that NP1300SBMCT3G is sourced from the original manufacturer or authorized distributors?
All NP1300SBMCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP1300SBMCT3G meets industry standards.
7.What is the process for return or replacement of NP1300SBMCT3G?
All NP1300SBMCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP1300SBMCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP1300SBMCT3G part is unused and in its original packaging.
Return procedure for NP1300SBMCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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