onsemi NP3100SCMCT3G
- Part No.:
- NP3100SCMCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP3100SCMCT3G.pdf
- Description:
- THYRISTOR 275V 400A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:3,673
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Product details
Overview
NP3100SCMCT3G from onsemi is a bidirectional ultra-low-capacitance thyristor surge protection device (TSPD) designed for telecom line protection in xDSL and T1/E1 interfaces. It features ±275 V repetitive peak off-state voltage (VDRM), ±350 V breakover voltage (V(BO)), 23 pF nominal off-state capacitance at 1 MHz, 4 V on-state voltage at 2.2 A, and 150 mA holding current - enabling transparent operation and low signal distortion in high-speed data lines.
For engineers reviewing the NP3100SCMCT3G datasheet, pinout, applications, or equivalent options, this device is selected for GR-1089-CORE and ITU-T K.20/K.21 compliant telecom surge protection where micro-capacitance, precise turn-on voltage, and high surge current capability are critical.
Technical Context
The NP3100SCMCT3G operates as a crowbar-type protector: it remains high-impedance (open-circuit) during normal operation (IDRM ≤ 5 µA at VDRM), then switches to low-impedance (short-circuit) when transient voltage exceeds V(BO), shunting surge energy to ground. Its bidirectional symmetric structure supports AC-coupled telecom lines without polarity concerns.
It delivers 150 A peak pulse surge current (IPPS1, 2×10 µs waveform), with thermal resistance RθJA = 90 °C/W and junction temperature range of −40 °C to +150 °C. The device complies with ULTRA LOW CAPACITANCE SMB package constraints and meets IEC 61000-4-5, GR-1089-CORE, and TIA-968-A surge immunity requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | ±275 V - ensures stable open-circuit behavior under 212 V peak ring voltage + 48 V battery margin in ADSL/T1 systems |
| V(BO) | ±350 V - guarantees maximum clamping voltage stays below protected circuit failure thresholds (e.g., SLIC or coupling capacitor ratings) |
| Co | 23 pF at 1 MHz / 2 Vdc - minimizes insertion loss and phase distortion in >10 Mbps DSL signals |
| VT | 4 V at 2.2 A pk - enables efficient surge conduction without excessive power dissipation in SMB footprint |
| IH | 150 mA - prevents latch-up by exceeding typical line feed current, ensuring automatic recovery post-surge |
| IPPS1 | 150 A (2×10 µs) - withstands lightning-induced surges per GR-1089-CORE Category A test profiles |
| TJ Range | −40 °C to +150 °C - supports operation in uncontrolled central office and outdoor cabinet environments |
Pinout & Package
NP3100SCMCT3G is housed in an SMB (DO-214AA, Case 403C) surface-mount package with two terminals: Anode and Cathode. The device is bidirectional; both terminals function identically under reverse/forward bias due to symmetrical thyristor construction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode | Thyristor gate-controlled terminal (bidirectional) | Connects to line (Tip/Ring); forms symmetrical crowbar path with Cathode during overvoltage |
| Cathode | Thyristor gate-controlled terminal (bidirectional) | Connects to line (Tip/Ring); identical functional role as Anode; no polarity assignment required |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low off-state capacitance | 23 pF - preserves signal integrity in broadband DSL/T1 links up to 2.048 Mbps without equalization penalty |
| Precise bidirectional breakover voltage | ±350 V (max) - enables deterministic clamping alignment with equipment failure margins and regulatory test limits |
| Low leakage transparency | IDRM ≤ 5 µA at ±275 V - eliminates DC loading on voice/data hybrid circuits and avoids false triggering |
| High surge current capability | 150 A (2×10 µs) - satisfies GR-1089-CORE Category A surge immunity without external current limiting |
| Pb-free RoHS-compliant packaging | SMB (DO-214AA) with matte tin lead finish - supports lead-free reflow (J-STD-020) and eliminates post-process cleaning |
Applications
| ADSL Central Office Line Card | T1/E1 Data Interface Protection |
|---|---|
Use Scenario: Protecting twisted-pair copper lines in DSLAM line cards exposed to induced lightning surges and power cross events. IC Role / Device Role / Timing Role: Bidirectional crowbar surge protector placed across Tip/Ring before SLIC and line transformer. Use Value: 23 pF capacitance prevents attenuation of upstream/downstream DSL bands; ±350 V V(BO) ensures clamping below SLIC absolute maximum rating (±380 V). |
Use Scenario: Safeguarding T1/E1 framer and transceiver ICs in telecom access equipment against longitudinal surges per GR-1089-CORE. IC Role / Device Role / Timing Role: Primary line-side surge suppressor mounted differential across transmit/receive pairs. Use Value: 150 A IPPS1 rating handles 10x160 µs surges without degradation; symmetric VDRM/V(BO) eliminates need for polarity-aware layout. |
| xDSL Customer Premises Equipment | Broadband Remote Terminal Units |
Use Scenario: Integrated surge protection in residential DSL modems and gateways operating on shared telephone lines. IC Role / Device Role / Timing Role: Secondary protection stage after gas discharge tube (GDT), providing fast-response clamping. Use Value: 4 V VT enables low-power dissipation during surge conduction; 150 mA IH exceeds typical POTS loop current, ensuring auto-recovery. |
Use Scenario: Protecting backhaul interfaces in fiber-to-the-node (FTTN) cabinets handling multiple T1/E1 feeds. IC Role / Device Role / Timing Role: Distributed surge suppression on each line pair within multi-channel line interface units (LIUs). Use Value: SMB package allows dense placement on high-pin-count PCBs; −40 °C to +150 °C TJ range supports fanless outdoor deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP2600SCMCT3G | VDRM = ±220 V, V(BO) = ±300 V - lower voltage rating than NP3100SCMCT3G | Suitable for 170 V peak systems (e.g., legacy T1 with lower ring voltage); insufficient for 275 V+ designs | Select NP2600SCMCT3G only if system VOP peak < 220 V and protected circuit failure threshold < 300 V |
| NP3500SCMCT3G | VDRM = ±320 V, V(BO) = ±400 V - higher voltage rating, same 23 pF Co and 4 V VT | Required for next-gen systems with >275 V operating margins or enhanced lightning immunity (e.g., rural CO deployments) | Choose NP3500SCMCT3G when VDRM margin must exceed 275 V or V(BO) headroom > 50 V is needed versus equipment rating |
Compared with NP2600SCMCT3G and NP3500SCMCT3G, the NP3100SCMCT3G provides optimal voltage coordination for standard ADSL/T1 systems with 212 V peak ring voltage and 350 V equipment failure thresholds - balancing clamping precision, surge margin, and signal fidelity without over-specifying.
Availability
NP3100SCMCT3G is available at Aetrix Electronics and suitable for xDSL central office line cards, T1/E1 data interface protection, and broadband remote terminal units requiring stable component supply, full traceability, and long-term lifecycle support.
Supply support for NP3100SCMCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and communications markets.
The NPMC Series - including NP3100SCMCT3G - was developed specifically for telecom line surge protection, targeting compliance with GR-1089-CORE, ITU-T K.20/K.21, and IEC 61000-4-5 while maintaining ultra-low capacitance for high-speed data integrity.
FAQ
What is the primary function of the NP3100SCMCT3G in a telecom circuit?
The NP3100SCMCT3G functions as a bidirectional crowbar-type surge protector. During normal operation, it presents high impedance (≤5 µA leakage at ±275 V). When a transient exceeds ±350 V, it switches to low-impedance conduction (4 V drop at 2.2 A), shunting surge current to ground. This protects downstream SLICs, transformers, and framer ICs in ADSL/T1 systems without distorting high-frequency signals due to its 23 pF capacitance. The NP3100SCMCT3G recovers automatically once line voltage returns below holding current threshold.
Does the NP3100SCMCT3G require external biasing or control circuitry?
No, the NP3100SCMCT3G operates passively and requires no external bias, control signals, or gate drive. It relies solely on intrinsic thyristor physics: voltage-dependent breakover triggers conduction when V(BO) is exceeded, and holding current (IH = 150 mA) determines recovery. This self-contained operation simplifies design, eliminates BOM cost for drivers or regulators, and enhances reliability. The NP3100SCMCT3G is directly soldered across Tip/Ring or differential data pairs with no supporting components needed.
How does the 23 pF off-state capacitance of NP3100SCMCT3G impact DSL signal performance?
The 23 pF off-state capacitance of NP3100SCMCT3G minimizes insertion loss and group delay variation across DSL frequency bands (up to 2.2 MHz for ADSL2+). At 1 MHz, this value contributes <0.1 dB attenuation and <1° phase shift in typical 100 Ω line impedance - preserving SNR and bit error rate. Unlike higher-capacitance MOVs or GDTs, the NP3100SCMCT3G avoids low-pass filtering of upstream channels, enabling full-bandwidth utilization without equalizer compensation. This makes the NP3100SCMCT3G suitable for VDSL2 and future G.fast deployments where signal fidelity is critical.
Can NP3100SCMCT3G be used in DC-powered telecom equipment?
Yes, the NP3100SCMCT3G is rated for continuous DC operation up to ±275 V (VDRM), making it compatible with DC-fed telecom systems such as remote terminal units and powered line cards. Its bidirectional symmetry ensures identical performance regardless of DC polarity, and its 150 mA holding current exceeds typical POTS loop feed currents (20–50 mA), guaranteeing automatic reset after surge clearance. The NP3100SCMCT3G's −40 °C to +150 °C junction temperature range further supports use in fanless, sealed enclosures common in outdoor DC-powered infrastructure.
What regulatory standards does NP3100SCMCT3G help satisfy?
The NP3100SCMCT3G is engineered to meet key telecom surge immunity standards including GR-1089-CORE (Categories A/B/C), ITU-T K.20/K.21/K.45, IEC 61000-4-5 (10/700 µs, 10/1000 µs waveforms), TIA-968-A, FCC Part 68, UL 1950, and EN 60950. Its 150 A peak surge rating (2×10 µs), precise ±350 V V(BO), and low capacitance enable system-level compliance without additional protection stages. Designers reference the NP3100SCMCT3G in safety documentation for telecom equipment certification, as onsemi provides full test reports validating these standards for the NPMC Series.
NP3100SCMCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 350V
- Voltage - Off State:
- 275V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- 400 A
- Current - Peak Pulse (10/1000µs):
- 100 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 33pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP3100SCMCT3G FAQ
1.How can I place an order for NP3100SCMCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP3100SCMCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP3100SCMCT3G reliable?
The price and inventory of NP3100SCMCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP3100SCMCT3G is usually 5 days.
3.What payment methods are accepted for NP3100SCMCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP3100SCMCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP3100SCMCT3G?
NP3100SCMCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP3100SCMCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP3100SCMCT3G?
For technical support, including NP3100SCMCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP3100SCMCT3G requirements.
6.How does Aetrix verify that NP3100SCMCT3G is sourced from the original manufacturer or authorized distributors?
All NP3100SCMCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP3100SCMCT3G meets industry standards.
7.What is the process for return or replacement of NP3100SCMCT3G?
All NP3100SCMCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP3100SCMCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP3100SCMCT3G part is unused and in its original packaging.
Return procedure for NP3100SCMCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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